- 10 Feb, 2021 38 commits
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Weili Qian authored
This patch fixes inconsistent of printing format with argument type. Signed-off-by:
Weili Qian <qianweili@huawei.com> Reviewed-by:
Zaibo Xu <xuzaibo@huawei.com> Signed-off-by:
Herbert Xu <herbert@gondor.apana.org.au>
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Weili Qian authored
There is no need to reset hardware when Corrected Error(CE) happens. Signed-off-by:
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Sihang Chen authored
There is no need to share IRQ among several devices, and set 'irqflag' as 0. Signed-off-by:
Sihang Chen <chensihang1@hisilicon.com> Signed-off-by:
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Weili Qian authored
Since the size of base number is 16 bits, update the value of 'QM_SQC_VFT_BASE_MASK_V2' as 'GENMASK(15, 0)'. Signed-off-by:
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Weili Qian authored
Add 'qp_stop_fail_cb' to ensure it is called as device is resetting. Signed-off-by:
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Weili Qian authored
Add waiting logic for resetting as removing driver, otherwise call trace will occur due to releasing resource. Signed-off-by:
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Arnd Bergmann authored
When CONFIG_CPUMASK_OFFSTACK is disabled, clang reports a warning about a bogus condition: drivers/crypto/marvell/octeontx2/otx2_cptlf.c:334:21: error: address of array 'lfs->lf[slot].affinity_mask' will always evaluate to 'true' [-Werror,-Wpointer-bool-conversion] if (lfs->lf[slot].affinity_mask) ~~ ~~~~~~~~~~~~~~^~~~~~~~~~~~~ In this configuration, the free_cpumask_var() function does nothing, so the condition could be skipped. When the option is enabled, there is no warning, but the check is also redundant because free_cpumask_var() falls back to kfree(), which is documented as ignoring NULL pointers. Remove the check to avoid the warning. Fixes: 64506017 ("crypto: octeontx2 - add LF framework") Signed-off-by:Arnd Bergmann <arnd@arndb.de> Reviewed-by:
Nathan Chancellor <nathan@kernel.org> Signed-off-by:
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Hui Tang authored
Enable x25519/x448/ecdh/ecdsa/sm2 algorithm on Kunpeng 930. Signed-off-by:
Hui Tang <tanghui20@huawei.com> Signed-off-by:
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Weili Qian authored
Enable PASID by setting 'sqc' and 'cqc' pasid bits per queue in Kunpeng 930. For Kunpeng 920, PASID is effective for all queues once set in SVA scenarios. Signed-off-by:
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Weili Qian authored
Calling 'dma_map_single' after the data is written to ensure that the cpu cache and dma cache are consistent. Signed-off-by:
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Hui Tang authored
Update since some special settings only for Kunpeng920. Signed-off-by:
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Hui Tang authored
HPRE of Kunpeng 930 is updated on cluster numbers, so we try to update this driver to make it running okay on Kunpeng920/Kunpeng930 chips. Signed-off-by:
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Xu Wang authored
Remove casting the values returned by dma_alloc_coherent. Signed-off-by:
Xu Wang <vulab@iscas.ac.cn> Signed-off-by:
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Daniele Alessandrelli authored
In ocs_aes_ccm_write_b0(), 'q' (the octet length of the binary representation of the octet length of the payload) is set to 'iv[0]', while it should be set to 'iv[0] & 0x7' (i.e., only the last 3 bits of iv[0] should be used), as documented in NIST Special Publication 800-38C: https://nvlpubs.nist.gov/nistpubs/Legacy/SP/nistspecialpublication800-38c.pdf In practice, this is not an issue, since 'iv[0]' is checked to be in the range [1-7] by ocs_aes_validate_inputs(), but let's fix the assignment anyway, in order to make the code more robust. Signed-off-by:
Daniele Alessandrelli <daniele.alessandrelli@intel.com> Signed-off-by:
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Bhaskar Chowdhury authored
s/optimzation/optimization/ Signed-off-by:
Bhaskar Chowdhury <unixbhaskar@gmail.com> Acked-by:
Randy Dunlap <rdunlap@infradead.org> Signed-off-by:
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Tian Tao authored
Use devm_hwrng_register to get rid of manual unregistration. Signed-off-by:
Tian Tao <tiantao6@hisilicon.com> Reviewed-by:
Sumit Garg <sumit.garg@linaro.org> Signed-off-by:
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Ard Biesheuvel authored
Instead of yielding from the bowels of the asm routine if a reschedule is needed, divide up the input into 4 KB chunks in the C glue. This simplifies the code substantially, and avoids scheduling out the task with the asm routine on the call stack, which is undesirable from a CFI/instrumentation point of view. Signed-off-by:
Ard Biesheuvel <ardb@kernel.org> Signed-off-by:
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Ard Biesheuvel authored
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Ard Biesheuvel authored
There is no need for elaborate yield handling in the bit-sliced NEON implementation of AES, given that skciphers are naturally bounded by the size of the chunks returned by the skcipher_walk API. So remove the yield calls from the asm code. Signed-off-by:
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Ard Biesheuvel authored
Instead of calling into kernel_neon_end() and kernel_neon_begin() (and potentially into schedule()) from the assembler code when running in task mode and a reschedule is pending, perform only the preempt count check in assembler, but simply return early in this case, and let the C code deal with the consequences. This reverts commit 6caf7adc. Signed-off-by:
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Ard Biesheuvel authored
Instead of calling into kernel_neon_end() and kernel_neon_begin() (and potentially into schedule()) from the assembler code when running in task mode and a reschedule is pending, perform only the preempt count check in assembler, but simply return early in this case, and let the C code deal with the consequences. This reverts commit 7edc86cb. Signed-off-by:
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Ard Biesheuvel authored
Instead of calling into kernel_neon_end() and kernel_neon_begin() (and potentially into schedule()) from the assembler code when running in task mode and a reschedule is pending, perform only the preempt count check in assembler, but simply return early in this case, and let the C code deal with the consequences. This reverts commit d82f37ab. Signed-off-by:
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Ard Biesheuvel authored
Instead of calling into kernel_neon_end() and kernel_neon_begin() (and potentially into schedule()) from the assembler code when running in task mode and a reschedule is pending, perform only the preempt count check in assembler, but simply return early in this case, and let the C code deal with the consequences. This reverts commit 7df8d164. Signed-off-by:
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Daniele Alessandrelli authored
The length ('len' parameter) passed to crypto_ecdh_decode_key() is never checked against the length encoded in the passed buffer ('buf' parameter). This could lead to an out-of-bounds access when the passed length is less than the encoded length. Add a check to prevent that. Fixes: 3c4b2390 ("crypto: ecdh - Add ECDH software support") Signed-off-by: -
Yang Li authored
Eliminate the following coccicheck warning: ./arch/powerpc/crypto/sha256-spe-glue.c:132:2-3: Unneeded semicolon Reported-by:
Abaci Robot <abaci@linux.alibaba.com> Signed-off-by:
Yang Li <yang.lee@linux.alibaba.com> Signed-off-by:
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Jiapeng Chong authored
Fix the following coccicheck warning: ./drivers/crypto/caam/debugfs.c:23:0-23: WARNING: caam_fops_u64_ro should be defined with DEFINE_DEBUGFS_ATTRIBUTE. ./drivers/crypto/caam/debugfs.c:22:0-23: WARNING: caam_fops_u32_ro should be defined with DEFINE_DEBUGFS_ATTRIBUTE. Reported-by:
Jiapeng Chong <jiapeng.chong@linux.alibaba.com> Reviewed-by:
Horia Geantă <horia.geanta@nxp.com> Signed-off-by:
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Ard Biesheuvel authored
Instead of using an alignmask of 0x3 to ensure 32-bit alignment of the Twofish input and output blocks, which propagates to mode drivers, and results in pointless copying on architectures that don't care about alignment, use the unaligned accessors, which will do the right thing on each respective architecture, avoiding the need for double buffering. Signed-off-by:
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Ard Biesheuvel authored
The fcrypt implementation uses memcpy() to access the input and output buffers so there is no need to set an alignmask. Signed-off-by:
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Ard Biesheuvel authored
Instead of using an alignmask of 0x3 to ensure 32-bit alignment of the CAST6 input and output blocks, which propagates to mode drivers, and results in pointless copying on architectures that don't care about alignment, use the unaligned accessors, which will do the right thing on each respective architecture, avoiding the need for double buffering. Signed-off-by:
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Ard Biesheuvel authored
Instead of using an alignmask of 0x3 to ensure 32-bit alignment of the CAST5 input and output blocks, which propagates to mode drivers, and results in pointless copying on architectures that don't care about alignment, use the unaligned accessors, which will do the right thing on each respective architecture, avoiding the need for double buffering. Signed-off-by:
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Ard Biesheuvel authored
Instead of using an alignmask of 0x3 to ensure 32-bit alignment of the Camellia input and output blocks, which propagates to mode drivers, and results in pointless copying on architectures that don't care about alignment, use the unaligned accessors, which will do the right thing on each respective architecture, avoiding the need for double buffering. Signed-off-by:
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Ard Biesheuvel authored
Instead of using an alignmask of 0x3 to ensure 32-bit alignment of the Blowfish input and output blocks, which propagates to mode drivers, and results in pointless copying on architectures that don't care about alignment, use the unaligned accessors, which will do the right thing on each respective architecture, avoiding the need for double buffering. Signed-off-by:
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Ard Biesheuvel authored
Instead of using an alignmask of 0x3 to ensure 32-bit alignment of the Serpent input and output blocks, which propagates to mode drivers, and results in pointless copying on architectures that don't care about alignment, use the unaligned accessors, which will do the right thing on each respective architecture, avoiding the need for double buffering. Signed-off-by:
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Ard Biesheuvel authored
It is not trivial to trace back why exactly the tnepres variant of serpent was added ~17 years ago - Google searches come up mostly empty, but it seems to be related with the 'kerneli' version, which was based on an incorrect interpretation of the serpent spec. In other words, nobody is likely to care anymore today, so let's get rid of it. Signed-off-by:
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Ard Biesheuvel authored
The Michael MIC driver uses the cra_alignmask to ensure that pointers presented to its update and finup/final methods are 32-bit aligned. However, due to the way the shash API works, this is no guarantee that the 32-bit reads occurring in the update method are also aligned, as the size of the buffer presented to update may be of uneven length. For instance, an update() of 3 bytes followed by a misaligned update() of 4 or more bytes will result in a misaligned access using an accessor that is not suitable for this. On most architectures, this does not matter, and so setting the cra_alignmask is pointless. On architectures where this does matter, setting the cra_alignmask does not actually solve the problem. So let's get rid of the cra_alignmask, and use unaligned accessors instead, where appropriate. Cc: <stable@vger.kernel.org> Signed-off-by:
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Jan Henrik Weinstock authored
Ensure cooldown period tolerance of 1% is actually accounted for. Fixes: ca3bff70 ("hwrng: timeriomem - Improve performance...") Signed-off-by:
Jan Henrik Weinstock <jan.weinstock@rwth-aachen.de> Signed-off-by:
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Geert Uytterhoeven authored
The Marvell OcteonTX2 CPT physical function PCI device is present only on OcteonTx2 SoC, and not available as an independent PCIe endpoint. Hence add a dependency on ARCH_THUNDER2, to prevent asking the user about this driver when configuring a kernel without OcteonTx2 platform support. Fixes: 5e8ce833 ("crypto: marvell - add Marvell OcteonTX2 CPT PF driver") Signed-off-by:
Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by:
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git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linuxHerbert Xu authored
Pull change from arm64 tree that's needed for crypto arm changes.
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- 05 Feb, 2021 2 commits
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Florian Fainelli authored
It is currently possible to build CONFIG_HW_RANDOM_PPC4XX=y with CONFIG_HW_RANDOM=m which would lead to the inability of linking with devm_hwrng_{register,unregister}. We cannot have the framework modular and the consumer of that framework built-in, so make that dependency explicit. Reported-by:kernel test robot <lkp@intel.com> Signed-off-by:
Florian Fainelli <f.fainelli@gmail.com> Signed-off-by:
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Herbert Xu authored
The crypto octeontx2 driver depends on the mbox code in the network tree. It tries to select the MBOX Kconfig option but that option itself depends on many other options which are not selected, e.g., CONFIG_NET_VENDOR_MARVELL. It would be inappropriate to select them all as randomly prompting the user for network options which would oterhwise be disabled just because a crypto driver has been enabled makes no sense. This patch fixes this by adding a dependency on NET_VENDOR_MARVELL. This makes the crypto driver invisible if the network option is off. If the crypto driver must be visible even without the network stack then the shared mbox code should be moved out of drivers/net. Reported-by:
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