1. 24 Mar, 2006 7 commits
    • Jack Steiner's avatar
      [IA64] Increase max node count on SN platforms · 4d357aca
      Jack Steiner authored
      Update configuration files with new CONFIG option.
      Signed-off-by: default avatarJack Steiner <steiner@sgi.com>
      Signed-off-by: default avatarTony Luck <tony.luck@intel.com>
      4d357aca
    • Jack Steiner's avatar
      [IA64] Increase max node count on SN platforms · a9de9835
      Jack Steiner authored
      Node number are kept in the cpu_to_node_map which is
      currently defined as u8. Change to u16 to accomodate
      larger node numbers.
      Signed-off-by: default avatarJack Steiner <steiner@sgi.com>
      Signed-off-by: default avatarTony Luck <tony.luck@intel.com>
      a9de9835
    • Jack Steiner's avatar
      [IA64] Increase max node count on SN platforms · 3ad5ef8b
      Jack Steiner authored
      Add support in IA64 acpi for platforms that support more than
      256 nodes. Currently, ACPI is limited to 256 nodes because the
      proximity domain number is 8-bits.
      
      Long term, we expect to use ACPI3.0 to support >256 nodes.
      This patch is an interim solution that works with platforms
      that pass the  high order bits of the proximity domain in
      "reserved" fields of the ACPI tables. This code is enabled
      ONLY on SN platforms.
      Signed-off-by: default avatarJack Steiner <steiner@sgi.com>
      Signed-off-by: default avatarTony Luck <tony.luck@intel.com>
      3ad5ef8b
    • Jack Steiner's avatar
      [IA64] Increase max node count on SN platforms · b354a838
      Jack Steiner authored
      Add a configuration option to allow the maximum
      number of nodes to be configurable for GENERIC or SN
      kernels.
      Signed-off-by: default avatarJack Steiner <steiner@sgi.com>
      Signed-off-by: default avatarTony Luck <tony.luck@intel.com>
      b354a838
    • Prarit Bhargava's avatar
      [IA64] Tollhouse HP: IA64 arch changes · f90aa8c4
      Prarit Bhargava authored
      arch/ia64/sn and include/asm-ia64/sn changes required to support Tollhouse
      system PCI hotplug, fixes the ia64_sn_sysctl_ioboard_get call, and introduces
      the PRF_HOTPLUG_SUPPORT feature bit.
      Signed-off-by: default avatarPrarit Bhargava <prarit@sgi.com>
      Signed-off-by: default avatarTony Luck <tony.luck@intel.com>
      f90aa8c4
    • Chen, Kenneth W's avatar
      [IA64] cleanup dig_irq_init · b17ea91a
      Chen, Kenneth W authored
      dig_irq_init is equivalent to machvec_noop, no need to define
      another empty function.
      Signed-off-by: default avatarKen Chen <kenneth.w.chen@intel.com>
      Signed-off-by: default avatarTony Luck <tony.luck@intel.com>
      b17ea91a
    • Russ Anderson's avatar
      [IA64] MCA recovery: kernel context recovery table · d2a28ad9
      Russ Anderson authored
      Memory errors encountered by user applications may surface
      when the CPU is running in kernel context.  The current code
      will not attempt recovery if the MCA surfaces in kernel
      context (privilage mode 0).  This patch adds a check for cases
      where the user initiated the load that surfaces in kernel
      interrupt code.
      
      An example is a user process lauching a load from memory
      and the data in memory had bad ECC.  Before the bad data
      gets to the CPU register, and interrupt comes in.  The
      code jumps to the IVT interrupt entry point and begins
      execution in kernel context.  The process of saving the
      user registers (SAVE_REST) causes the bad data to be loaded
      into a CPU register, triggering the MCA.  The MCA surfaces in
      kernel context, even though the load was initiated from
      user context.
      
      As suggested by David and Tony, this patch uses an exception
      table like approach, puting the tagged recovery addresses in
      a searchable table.  One difference from the exception table
      is that MCAs do not surface in precise places (such as with
      a TLB miss), so instead of tagging specific instructions,
      address ranges are registers.  A single macro is used to do
      the tagging, with the input parameter being the label
      of the starting address and the macro being the ending
      address.  This limits clutter in the code.
      
      This patch only tags one spot, the interrupt ivt entry.
      Testing showed that spot to be a "heavy hitter" with
      MCAs surfacing while saving user registers.  Other spots
      can be added as needed by adding a single macro.
      
      Signed-off-by: Russ Anderson (rja@sgi.com)
      Signed-off-by: default avatarTony Luck <tony.luck@intel.com>
      d2a28ad9
  2. 23 Mar, 2006 7 commits
  3. 22 Mar, 2006 26 commits