Pull improved Marvel Armada 7K/8K cp110 clk support from Gregory CLEMENT:

We got more information about the clock controllers and the clock tree
of the CP110 part that we find in the Marvell Armada 7K/8K SoCs. The
clk driver is modified accordingly from this new information.

* 'clk-cp110' of git://git.infradead.org/linux-mvebu:
  clk: mvebu: cp110: add sdio clock to cp-110 system controller
  clk: mvebu: cp110: introduce a new binding
  clk: mvebu: cp110: do not depend anymore of the *-clock-output-names
  clk: mvebu: cp110: make failure labels more meaningful

The smplsel bits for the SDMMC clock on Arria10 and Stratix10 platforms are
offset by 1 additional bit.

Add a new macro SYSMGR_SDMMC_CTRL_SET_AS10 for usage on the Arria10 and
Stratix10 platforms.

Fixes: 5611a5ba ("clk: socfpga: update clk.h so for Arria10 platform to use")
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>

The timer will register into system at very early phase at kernel boot;
if timer needs to use clock, the clock should be get ready in function
of_clk_init() so later the timer driver probe can retrieve clock
successfully. This is finished in below flow on arm64:

  start_kernel()
    `-> time_init()
          `-> of_clk_init(NULL)    => register timer's clock
          `-> clocksource_probe()  => register timer

On Hi3660 the sp804 timer uses clock "osc32k", this clock is registered
as platform driver rather than CLK_OF_DECLARE_DRIVER method. As result,
sp804 timer probe returns failure due if cannot bind clock properly.

To fix the failure, this patch is to split crgctrl clocks into two
subsets. One part is for fixed_rate_clks which includes pre-defined
fixed rate clocks, and "osc32k" clock is in this category; So we change
their registration to CLK_OF_DECLARE_DRIVER method, as result the clocks
can be registered ahead with function of_clk_init() and timer driver can
bind timer clock successfully; the rest of the crgctrl clocks are still
registered by the probe of the platform driver.

This patch also adds checking for all crgctrl clocks registration and
print out log if any clock has failure.
Signed-off-by: Leo Yan <leo.yan@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>

This commit updates the CP110 system controller driver to add the
definition for a missing clock.

The SDIO clock is dedicated driving the SDHCI interface and its frequency
is 400MHz (2/5 of PLL source clock).

The SDIO interface should be bound to this clock and not the core clock
as in the older code.
Using the wrong clock lead to a maximum SDHCI frequency of 250 Mhz, while
the HW really supports up to 400 Mhz.

This patch also fixes the NAND clock relationship documentation.
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
[gregory.clement@free-electrons.com:
- use sdio instead of emmc to name the clock]
Reviewed-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>

The initial intent when the binding of the cp110 system controller was to
have one flat node. The idea being that what is currently a clock-only
driver in drivers would become a MFD driver, exposing the clock, GPIO and
pinctrl functionality. However, after taking a step back, this would lead
to a messy binding. Indeed, a single node would be a GPIO controller,
clock controller, pinmux controller, and more.

This patch adopts a more classical solution of a top-level syscon node
with sub-nodes for the individual devices. The main benefit will be to
have each functional block associated to its own sub-node where we can
put its own properties.

The introduction of the Armada 7K/8K is still in the early stage so the
plan is to remove the old binding. However, we don't want to break the
device tree compatibility for the few devices already in the field. For
this we still keep the support of the legacy compatible string with a big
warning in the kernel about updating the device tree.
Reviewed-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>

Using the *-clock-output-names property was a convenient way to have a
unique name for each clock even when there are multiple cp110 blocks
as we can find on Armada 8K.

However it has some drawbacks: the main one being a stronger link than
necessary between the driver and the device tree. For example the clock
name can't be changed, removed or moved. It is still the early stage of
introduction of the Armada 7K/8K and the hardware is still not totally
documented, especially for the clock part. By removing the use of
*-clock-output-names it will be easier to add new clocks without breaking
the compatibility.

The name of each clock is now created by using its physical address as a
prefix (as it was done for the platform device names). Thanks to this we
have an automatic way to compute a unique name.
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>

Pull Amlogic clk driver updates from Jerome Brunet:

 * Expose more clock gate on meson8 (SAR ADC, RNG, USB, SDIO, ETH)
 * Add new compatible to the meson8 clock controller for meson8b
 * Add missing parents to gxbb clk81

* tag 'meson-clk-for-4.13-2' of git://github.com/BayLibre/clk-meson:
  clk: meson: gxbb: add all clk81 parents
  clk: meson: meson8b: add compatibles for Meson8 and Meson8m2
  clk: meson8b: export the ethernet gate clock
  clk: meson8b: export the USB clocks
  clk: meson8b: export the gate clock for the HW random number generator
  clk: meson8b: export the SDIO clock
  clk: meson8b: export the SAR ADC clocks

* 'for-4.13-ti-clkctrl' of https://github.com/t-kristo/linux-pm:
  clk: ti: omap4: add clkctrl clock data
  dt-bindings: clk: add omap4 clkctrl definitions
  clk: ti: add support for clkctrl clocks
  Documentation: dt-bindings: Add binding documentation for TI clkctrl clocks

It isn't used outside of this file right now.
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>

Merge tag 'sunxi-clk-for-4.13' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into clk-next

Pull Allwinner clock patches from Maxime Ripard:

Some new clock units are supported, for the display clocks unsed in the
newer SoCs, and the A83T PRCM.

There is also a bunch of minor fixes for clocks that are not used by
anyone, and reworks needed by drivers that will land in 4.13.

* tag 'sunxi-clk-for-4.13' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux: (21 commits)
  clk: sunxi-ng: Move all clock types to a library
  clk: sunxi-ng: a83t: Add support for A83T's PRCM
  dt-bindings: clock: sunxi-ccu: Add compatible string for A83T PRCM
  clk: sunxi-ng: select SUNXI_CCU_MULT for sun8i-a83t
  clk: sunxi-ng: a83t: Fix audio PLL divider offset
  clk: sunxi-ng: a83t: Fix PLL lock status register offset
  clk: sunxi-ng: Add driver for A83T CCU
  clk: sunxi-ng: Support multiple variable pre-dividers
  dt-bindings: clock: sunxi-ccu: Add compatible string for A83T CCU
  clk: sunxi-ng: de2: fix wrong pointer passed to PTR_ERR()
  clk: sunxi-ng: sun5i: Export video PLLs
  clk: sunxi-ng: mux: Re-adjust parent rate
  clk: sunxi-ng: mux: Change pre-divider application function prototype
  clk: sunxi-ng: mux: split out the pre-divider computation code
  clk: sunxi-ng: mux: Don't just rely on the parent for CLK_SET_RATE_PARENT
  clk: sunxi-ng: div: Switch to divider_round_rate
  clk: sunxi-ng: Pass the parent and a pointer to the clocks round rate
  clk: divider: Make divider_round_rate take the parent clock
  clk: sunxi-ng: explicitly include linux/spinlock.h
  clk: sunxi-ng: add support for DE2 CCU
  ...

Remove the FIXME on clk81 mux and add all the documented parents
Acked-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>

Add data for omap4 clkctrl clocks, and register it within the clkctrl
driver.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>

Contains offsets for all omap4 clkctrl main and optional clocks.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>

Previously, hwmod core has been used for controlling the hwmod level
clocks directly. This has certain drawbacks, like being unable to share
the clocks for multiple users, missing usecounting and generally being
totally incompatible with the common clock framework.

This patch adds support for clkctrl clocks for addressing the above
issues. These support the modulemode handling, which will replace the
direct hwmod clkctrl linkage. Any optional clocks are also supported,
gate, mux and divider.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>

Texas Instruments omap variant SoCs starting with omap4 have a clkctrl
clock controller instance for each interconnect target module. The clkctrl
controls functional and interface clocks for the module.

The clkctrl clocks are currently handled by arch/arm/mach-omap2 hwmod code.
With this binding and a related clock device driver we can start moving the
clkctrl clock handling to live in drivers/clk/ti.

Note that this binding allows keeping the clockdomain related parts out of
drivers/clock. The CLKCTCTRL and DYNAMICDEP registers can be handled by
a separate driver in drivers/soc/ti and genpd. If the clockdomain driver
needs to know it's clocks, we can just set the the clkctrl device
instances to be children of the related clockdomain device.

Each clkctrl clock can have multiple optional gate clocks, and multiple
optional mux clocks. To represent this in device tree, it seems that
it is best done using four clock cells #clock-cells = <2> property.

The reasons for using #clock-cells = <2> are:

1. We need to specify the clkctrl offset from the instance base. Otherwise
   we end up with a large number of device tree nodes that need to be
   patched when new clocks are discovered in a clkctrl clock with minor
   hardware revision changes for example

2. On omap5 CM_L3INIT_USB_HOST_HS_CLKCTRL has ten OPTFCLKEN bits. So we
   need to use a separate cell for optional gate clocks to avoid address
   space conflicts

There is probably no need to list input clocks for each clkctrl clock
instance in the binding. If we want to add them, the standard clocks
binding can be used for that.

For hardware reference, see omap4430 TRM "Table 3-1312. L4PER_CM2 Registers
Mapping Summary" for example. It shows one instance of a clkctrl clock
controller with multiple clkctrl registers.

Cc: Paul Walmsley <paul@pwsan.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>

* clk-fixes:
  clk: sunxi-ng: a64: Export PLL_PERIPH0 clock for the PRCM
  clk: sunxi-ng: h3: Export PLL_PERIPH0 clock for the PRCM
  dt-bindings: clock: sunxi-ccu: Add pll-periph to PRCM's needed clocks
  clk: sunxi-ng: enable SUNXI_CCU_MP for PRCM
  clk: sunxi-ng: v3s: Fix usb otg device reset bit
  clk: sunxi-ng: a31: Correct lcd1-ch1 clock register offset

Merge tag 'sunxi-clk-fixes-for-4.12' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into clk-fixes

Allwinner clock fixes for 4.12

Some fixes that fix some bindings that went in 4.12, fix a few reset and
clock offsets and a build error fix

* tag 'sunxi-clk-fixes-for-4.12' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux:
  clk: sunxi-ng: a64: Export PLL_PERIPH0 clock for the PRCM
  clk: sunxi-ng: h3: Export PLL_PERIPH0 clock for the PRCM
  dt-bindings: clock: sunxi-ccu: Add pll-periph to PRCM's needed clocks
  clk: sunxi-ng: enable SUNXI_CCU_MP for PRCM
  clk: sunxi-ng: v3s: Fix usb otg device reset bit
  clk: sunxi-ng: a31: Correct lcd1-ch1 clock register offset

Merge tag 'clk-v4.13-samsung' of git://git.kernel.org/pub/scm/linux/kernel/git/snawrocki/clk into clk-next

Pull samsung clk driver updates from Sylwester Nawrocki

 - conversion to the clk_hw API
 - definitions and fixes of exynos5420 SoC audio subsystem
   related clocks

* tag 'clk-v4.13-samsung' of git://git.kernel.org/pub/scm/linux/kernel/git/snawrocki/clk:
  clk: samsung: exynos542x: Add EPLL rate table
  clk: samsung: Add missing exynos5420 audio related clocks
  clk: samsung: Add enable/disable operation for PLL36XX clocks
  clk: samsung: s5pv210-audss: Convert to the new clk_hw API
  clk: samsung: exynos-clkout: Convert to the new clk_hw API
  clk: samsung: exynos-audss: Convert to the new clk_hw API
  clk: samsung: Convert common drivers to the new clk_hw API
  clk: samsung: Add local variable to match its purpose
  clk: samsung: Remove dead code

Merge tag 'v4.13-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-next

Pull rockchip clk driver updates from Heiko Stuebner:

One new clock controller for the rk3128 soc, a fixup for the rk3228 cpuclk
table and the usual bunch of some new clock-ids and some clocks marked as
critical.

* tag 'v4.13-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
  clk: rockchip: mark some special clk as critical on rk3368
  clk: rockchip: mark noc and some special clk as critical on rk3288
  clk: rockchip: mark noc and some special clk as critical on rk3228
  clk: rockchip: mark pclk_ddrupctl as critical_clock on rk3036
  clk: rockchip: add clock controller for rk3128
  dt-bindings: add bindings for rk3128 clock controller
  clk: rockchip: export more rk3228 clocks ids
  clk: rockchip: add ids for rk3399 testclks used for camera handling
  clk: rockchip: add dt-binding header for rk3128
  clk: rockchip: fix up the RK3228 clk cpu setting table
  clk: rockchip: add clock-ids for more rk3228 clocks
  clk: rockchip: add ids for camera on rk3399

In K2G, the clock handling is done through firmware executing on a
separate core. Linux kernel needs to communicate to the firmware
through TI system control interface to access any power management
related resources, including clocks.

The keystone sci-clk driver does this, by communicating to the
firmware through the TI SCI driver. The driver adds support for
registering clocks through DT, and basic required clock operations
like prepare/get_rate, etc.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
[sboyd@codeaurora.org: Make ti_sci_init_clocks() static]
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>

Add a clock implementation, TI SCI clock, that will hook to the common
clock framework, and allow each clock to be controlled via TI SCI
protocol.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>

The clock controller on Meson8, Meson8b and Meson8m2 is very similar
based on the code from the Amlogic GPL kernel sources. Add separate
compatibles for each SoC to make sure that we can easily implement
all the small differences for each SoC later on.

In general the Meson8 and Meson8m2 seem to be almost identical as they
even share the same mach-meson8 directory in Amlogic's GPL kernel
sources.
The main clocks on Meson8, Meson8b and Meson8m2 are very similar,
because they are all using the same PLL values, 90% of the clock gates
are the same (the actual diffstat of the mach-meson8/clock.c and
mach-meson8b/clock.c files is around 30 to 40 lines, when excluding
all commented out code).
The difference between the Meson8 and Meson8b clock gates seem to be:
- Meson8 has AIU_PCLK, HDMI_RX, VCLK2_ENCT, VCLK2_ENCL, UART3,
  CSI_DIG_CLKIN gates which don't seem to be available on Meson8b
- the gate on Meson8 for bit 7 seems to be named "_1200XXX" instead
  of "PERIPHS_TOP" (on Meson8b)
- Meson8b has a SANA gate which doesn't seem to exist on Meson8 (or
  on Meson8 the same bit is used by the UART3 gate in Amlogic's GPL
  kernel sources)
None of these gates is added for now, since it's unclear whether these
definitions are actually correct (the VCLK2_ENCT gate for example is
defined, but only used in some commented block).

The main difference between all three SoCs seem to be the video (VPU)
clocks. Apart from different supported clock rates (according to vpu.c
in mach-meson8 and mach-meson8b from Amlogic's GPL kernel sources) the
most notable difference is that Meson8m2 has a GP_PLL clock and a mux
(probably the same as on the Meson GX SoCs) to support glitch-free
(clock rate) switching.
None of these VPU clocks are not supported by our mainline meson8b
clock driver yet though.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Kevin Hilman <khilman@baylibre.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>

Export the ethernet gate clock to the dt-bindings.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Acked-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>

Export the USB related clocks (for the USB controller and the USB2 PHYs)
so they can be used in the dt-bindings.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Acked-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>

This exports the clock so it can be used in the dt-bindings.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Acked-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>

Export the SDIO clock so it can be used in the dt-bindings.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Acked-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>

Export the clocks for the SAR ADC so they can be used in the
dt-bindings.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Acked-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>

A specific clock rate table is added for EPLL so it is possible
to set frequency of the EPLL output clock as multiple of various
audio sampling rates.
Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>

This patch adds missing definitions of mux clocks required for using
EPLL as the audio subsystem root clock on exynos5420/exynos5422 SoCs.
Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com>
Tested-by: Chanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>

The existing enable/disable ops for PLL35XX are made more generic
and used also for PLL36XX. This fixes issues in the kernel with
PLL36XX PLLs when the PLL has not been already enabled by bootloader.
Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com>
Tested-by: Chanwoo Choi <cw00.choi@samsung.com>
Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>

Clock providers should use the new struct clk_hw based API, so convert
Samsung S5PV210 Audio Subsystem clock provider to the new approach.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>

Clock providers should use the new struct clk_hw based API, so convert
Exynos CLKOUT clock provider to the new approach.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>

Clock providers should use the new struct clk_hw based API, so convert
Exynos Audio Subsystem clock provider to the new approach.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>

Clock providers should use the new struct clk_hw based API, so convert
Samsung clock providers and their helper functions to the new approach.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>

Add new variable to avoid using clk pointer for different purposes across
the exynos_register_cpu_clock() function. This will help in future rewrite
for the new clk_hw API.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>

samsung_clk_register_pll2550x() function is not used anymore,
so remove its declaration.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>

We've run into kconfig missing dependency errors in the sunxi-ng
code a couple times now. Each time the fix is to find the missing
select statement and add it to the Kconfig entry for a particular
SoC driver. Given that all this code is builtin (non-modular) we
don't need to do this complicated dependency tracking in Kconfig.
Instead we can move all the "library"ish code to be compiled as
lib-y instead of obj-y, let the linker throw away unused code in
the resulting vmlinux, and drop all the Kconfig stuff we use to
track clock types.
Suggested-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
[Maxime: added lib.a to obj-y, added the comment]
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>

The A83T's PRCM has the same set of clocks and resets as the A64.
However, a few dividers are different. And due to the lack of a low
speed 32.768 kHz oscillator, a few of the clock parents are different.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>

The A83T's PRCM has the same set of clocks and resets as the A64.
However, a few dividers are different. And due to the lack of a low
speed 32.768 kHz oscillator, a few of the clock parents are different.

The PRCM also has controls for various power domains. These are not
supported yet.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>