- 22 Aug, 2023 8 commits
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Dmitry Baryshkov authored
Migrate legacy bindings (described in qcom,ipq8074-qmp-pcie-phy.yaml) to qcom,sc8280xp-qmp-pcie-phy.yaml. This removes a need to declare the child PHY node or split resource regions. Signed-off-by:
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by:
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20230820142035.89903-2-dmitry.baryshkov@linaro.orgSigned-off-by:
Vinod Koul <vkoul@kernel.org>
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Alexander Stein authored
This adds an error message if getting vbus failed for some reason, -EPROBE_DEFER is handled appropriately as well and adds a nice information to debugfs. Signed-off-by:
Alexander Stein <alexander.stein@ew.tq-group.com> Link: https://lore.kernel.org/r/20230816080256.611380-1-alexander.stein@ew.tq-group.comSigned-off-by:
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Varadarajan Narayanan authored
Add the M31 USB2 phy driver for the USB M31 PHY (https://www.m31tech.com) found in Qualcomm IPQ5018, IPQ5332 SoCs. Signed-off-by:
Varadarajan Narayanan <quic_varada@quicinc.com> Reviewed-by:
Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/c8821bb0124a54cc774a2ff7b9c40df28eb7711e.1691999761.git.quic_varada@quicinc.comSigned-off-by:
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Varadarajan Narayanan authored
Document the M31 USB2 phy present in IPQ5332. Reviewed-by:
Sricharan Ramabadhran <quic_srichara@quicinc.com> Signed-off-by:
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Jagan Teki authored
Add support for Rockchip RV1126 DSI-DPHY. The existing 2.5GHz phy timing table added for RK3568 is working as it is for RV1126 as well. Signed-off-by:
Jagan Teki <jagan@edgeble.ai> Reviewed-by:
Heiko Stuebner <heiko@sntech.de> Link: https://lore.kernel.org/r/20230731110012.2913742-5-jagan@edgeble.aiSigned-off-by:
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Jagan Teki authored
Document a compatible string for the rv1126 dsi-dphy. Signed-off-by:
Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20230731110012.2913742-4-jagan@edgeble.aiSigned-off-by:
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Eugen Hristev authored
The pattern for the nodename only allows t-phy@... , however, for the case when the t-phy has no `reg` and only `ranges` (basically when the t-phy is just a parent node), dtc will throw this warning: Warning (unit_address_vs_reg): /t-phy@1a243000: node has a unit name, but no reg or ranges property For a node like this: sata_phy: t-phy@1a243000 { ranges; sata_port: sata-phy@1a243000 { reg = <0 0x1a243000 0 0x0100>; }; }; it is normal that the parent node 't-phy' would be without any address, as in: sata_phy: t-phy { ranges; sata_port: sata-phy@1a243000 { reg = <0 0x1a243000 0 0x0100>; }; }; because being just a holder it does not have its own reg. However the binding does not allow such a name for the t-phy, so with this patch, making the `@[0-9a-f]+` part optional, such node is possible. Signed-off-by:Eugen Hristev <eugen.hristev@collabora.com> Acked-by:
Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20230814093931.9298-1-eugen.hristev@collabora.comSigned-off-by:
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Krzysztof Kozlowski authored
'soc_id' is an enum, thus cast of pointer on 64-bit compile test with W=1 causes: phy-meson-g12a-usb2.c:322:17: error: cast to smaller integer type 'enum meson_soc_id' from 'const void *' [-Werror,-Wvoid-pointer-to-enum-cast] Signed-off-by:
Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20230810091310.70231-1-krzysztof.kozlowski@linaro.orgSigned-off-by:
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- 11 Aug, 2023 7 commits
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Krzysztof Kozlowski authored
'version' is an enum, thus cast of pointer on 64-bit compile test with W=1 causes: phy-pxa-usb.c:299:26: error: cast to smaller integer type 'enum pxa_usb_phy_version' from 'const void *' [-Werror,-Wvoid-pointer-to-enum-cast] Signed-off-by:
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Krzysztof Kozlowski authored
'version' is an enum, thus cast of pointer on 64-bit compile test with W=1 causes: phy-bcm-sr-usb.c:314:13: error: cast to smaller integer type 'enum bcm_usb_phy_version' from 'const void *' [-Werror,-Wvoid-pointer-to-enum-cast] Signed-off-by:
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Krzysztof Kozlowski authored
'family' is an enum, thus cast of pointer on 64-bit compile test with W=1 causes: drivers/phy/broadcom/phy-bcm-ns-usb3.c:209:17: error: cast to smaller integer type 'enum bcm_ns_family' from 'const void *' [-Werror,-Wvoid-pointer-to-enum-cast] Signed-off-by:
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Krzysztof Kozlowski authored
'version' is an enum, thus cast of pointer on 64-bit compile test with W=1 causes: phy-brcm-sata.c:775:19: error: cast to smaller integer type 'enum brcm_sata_phy_version' from 'const void *' [-Werror,-Wvoid-pointer-to-enum-cast] Signed-off-by:
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Rohit Agarwal authored
Add a dt-bindings compatible string for the Qualcomm's PM7550BA PMIC. Signed-off-by:
Rohit Agarwal <quic_rohiagar@quicinc.com> Reviewed-by:
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Lukas Bulwahn authored
Commit f8aa6608 ("phy: starfive: Add mipi dphy rx support") adds the MAINTAINERS section STARFIVE JH7110 DPHY RX DRIVER referring to 'phy-starfive-dphy-rx.c', but the file actually added in this commit is named 'phy-jh7110-dphy-rx.c'. Correct the file entry in STARFIVE JH7110 DPHY RX DRIVER. Signed-off-by:
Lukas Bulwahn <lukas.bulwahn@gmail.com> Reviewed-by:
Changhuang Liang <changhuang.liang@starfivetech.com> Link: https://lore.kernel.org/r/20230731114856.14401-1-lukas.bulwahn@gmail.comSigned-off-by:
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Dmitry Baryshkov authored
The conversion commit 7559e757 ("phy: Explicitly include correct DT includes") misses offsets configuration for sm8150 (most likely it was developed separately from the series adding HS G4 support and was not adapted for the sm8150/sm8250 configuration split). Add missing offsets to sm8150_ufsphy_cfg. Fixes: 7559e757 ("phy: Explicitly include correct DT includes") Signed-off-by:
Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20230731111009.3998089-1-dmitry.baryshkov@linaro.orgSigned-off-by:
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- 26 Jul, 2023 1 commit
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Geert Uytterhoeven authored
The various StarFive PHYs are only present on StarFive SoCs. Hence add a dependency on ARCH_STARFIVE, to prevent asking the user about these drivers when configuring a kernel without StarFive SoC support. Signed-off-by:
Geert Uytterhoeven <geert+renesas@glider.be> Acked-by:
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- 25 Jul, 2023 1 commit
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Vinod Koul authored
the startfive phy drivers use devm_platform_ioremap_resource() which on some archs (s390) is not present. So make the drivers depend on HAS_IOMEM Fixes: f8aa6608 ("phy: starfive: Add mipi dphy rx support") Reported-by:
kernel test robot <lkp@intel.com> Closes: https://lore.kernel.org/oe-kbuild-all/202307250509.oeudxG28-lkp@intel.com/Reviewed-by:
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- 24 Jul, 2023 8 commits
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Dmitry Baryshkov authored
Add separate device entry for Combo USB+DP QMP PHY on sc7280 platform. Reviewed-by:
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Dmitry Baryshkov authored
In order to support newer style bindings for combo PHYs, populate offsets for all Combo QMP PHY configurations. Reviewed-by:
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Dmitry Baryshkov authored
For the existing PHYs for new binding we are going to drop ref_clk_src clock and always use ref clock. Rather than introducing additional code to handle legacy vs current bindings (and clock names), use devm_clk_bulk_get_optional() when new bindings are used and devm_clk_bulk_get_all() when legacy bindings are in place. Signed-off-by:
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Dmitry Baryshkov authored
Migrate legacy bindings (described in qcom,sc7180-qmp-usb3-dp-phy.yaml) to qcom,sc8280xp-qmp-usb43dp-phy.yaml. This removes a need to declare the child PHY node or split resource regions. Reviewed-by:
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Yang Li authored
./drivers/phy/tegra/xusb.c: linux/platform_device.h is included more than once. Reported-by:
Abaci Robot <abaci@linux.alibaba.com> Closes: https://bugzilla.openanolis.cn/show_bug.cgi?id=5930Signed-off-by:
Yang Li <yang.lee@linux.alibaba.com> Acked-by:
Thierry Reding <treding@nvidia.com> Link: https://lore.kernel.org/r/20230719003614.5506-1-yang.lee@linux.alibaba.comSigned-off-by:
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Changhuang Liang authored
Add mipi dphy rx support for the StarFive JH7110 SoC. It is used to transfer CSI camera data. Signed-off-by:
Minda Chen <minda.chen@starfivetech.com> Link: https://lore.kernel.org/r/20230718070803.16660-3-changhuang.liang@starfivetech.comSigned-off-by:
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Changhuang Liang authored
StarFive SoCs like the jh7110 use a MIPI D-PHY RX controller based on a M31 IP. Add a binding for it. Signed-off-by:
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Dan Carpenter authored
This is using the wrong pointer, "phy->regs" vs "phy->phy". Fixes: fd097f48 ("phy: starfive: Add JH7110 PCIE 2.0 PHY driver") Signed-off-by:
Dan Carpenter <dan.carpenter@linaro.org> Link: https://lore.kernel.org/r/3cc81f2a-efd7-4ef7-ae6b-e38c91efe153@moroto.mountainSigned-off-by:
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- 18 Jul, 2023 3 commits
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Sebastian Reichel authored
When the RK3568 PCIe v3 PHY supported has been upstreamed, RK3588 support was included, but the DT binding does not reflect this. This adds the missing bits. Reviewed-by:
Sebastian Reichel <sebastian.reichel@collabora.com> Link: https://lore.kernel.org/r/20230717173512.65169-2-sebastian.reichel@collabora.comSigned-off-by:
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Mrinmay Sarkar authored
Add support for dual and four lane PHY found on sa8755p platform. Signed-off-by:
Mrinmay Sarkar <quic_msarkar@quicinc.com> Link: https://lore.kernel.org/r/1689311319-22054-5-git-send-email-quic_msarkar@quicinc.comSigned-off-by:
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Mrinmay Sarkar authored
Add devicetree YAML binding for Qualcomm QMP PCIe PHY for SA8775p platform. Signed-off-by:
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- 17 Jul, 2023 1 commit
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Rob Herring authored
The DT of_device.h and of_platform.h date back to the separate of_platform_bus_type before it as merged into the regular platform bus. As part of that merge prepping Arm DT support 13 years ago, they "temporarily" include each other. They also include platform_device.h and of.h. As a result, there's a pretty much random mix of those include files used throughout the tree. In order to detangle these headers and replace the implicit includes with struct declarations, users need to explicitly include the correct includes. Signed-off-by:
Sergio Paracuellos <sergio.paracuellos@gmail.com> Link: https://lore.kernel.org/r/20230714174841.4061919-1-robh@kernel.orgSigned-off-by:
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- 14 Jul, 2023 1 commit
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Andrew Davis authored
If the parent node is not a syscon type, then fallback and check if we can get a regmap from our own node. This no longer forces us to make the parent of this node a syscon node when that might not be appropriate. Signed-off-by:
Andrew Davis <afd@ti.com> Reviewed-by:
Roger Quadros <rogerq@ti.com> Reviewed-by:
Siddharth Vadapalli <s-vadapalli@ti.com> Link: https://lore.kernel.org/r/20230713200957.134480-1-afd@ti.comSigned-off-by:
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- 12 Jul, 2023 10 commits
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Sean Anderson authored
Due to limited available frequency ratios, the reference clock rate may not be exactly the same as the required rate. Allow a small (100 ppm) deviation. Signed-off-by:
Sean Anderson <sean.anderson@seco.com> Link: https://lore.kernel.org/r/20230711194542.898230-1-sean.anderson@seco.comSigned-off-by:
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Dmitry Baryshkov authored
Populate offsets configuration for the rest of UFS PHYs to make it possible to switch them to the new (single-node) bindings style. Reviewed-by:
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Dmitry Baryshkov authored
Migrate legacy bindings (described in qcom,msm8996-qmp-ufs-phy.yaml) to qcom,sc8280xp-qmp-ufs-phy.yaml. This removes a need to declare the child PHY node or split resource regions. Reviewed-by:
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Minda Chen authored
Add Starfive JH7110 SoC PCIe 2.0 PHY driver support. PCIe 2.0 PHY default connect to PCIe controller. PCIe PHY can connect to USB 3.0 controller. Signed-off-by:
Roger Quadros <rogerq@kernel.org> Link: https://lore.kernel.org/r/20230629075115.11934-5-minda.chen@starfivetech.comSigned-off-by:
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Minda Chen authored
Add Starfive JH7110 SoC USB 2.0 PHY driver support. USB 2.0 PHY default connect to Cadence USB controller. Signed-off-by:
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Minda Chen authored
Add StarFive JH7110 SoC PCIe 2.0 PHY dt-binding. PCIe PHY0 (phy@10210000) can be used as USB 3.0 PHY. Signed-off-by:
Hal Feng <hal.feng@starfivetech.com> Reviewed-by:
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Minda Chen authored
Add StarFive JH7110 SoC USB 2.0 PHY dt-binding. Signed-off-by:
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Marcin Wierzbicki authored
Add single link SGMII register configuration for no SSC for cdns,sierra-phy-t0 compatibility string. The configuration is based on Sierra Programmer's Guide and validated in Cisco CrayAR SoC. Co-developed-by:
Bartosz Wawrzyniak <bwawrzyn@cisco.com> Signed-off-by:
Marcin Wierzbicki <mawierzb@cisco.com> Link: https://lore.kernel.org/r/20230626105533.2999966-1-mawierzb@cisco.comSigned-off-by:
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Alex Bee authored
This adds a bunch of new pixel clock- and tmds rates to the pre-pll table which are required to get more VESA and some DMT rates working. It has been completely re-calculated to match the min- and max-vco of (750 MHz - 3.2 GHz) requirements. If more than one configuration would have been possible the lowest fbdiv and refdiv (and therefore lowest vco rate) has been preferred. It's important to note, that RK3228 version of the phy does not support fractional dividers. To support the most possible rates for this version also in both 8-bit and 10-bit variant, some rates are not exact. The maximum deviation of the pixel clock is 0.26, which perfectly fits into VESA DMT recommendation of 0.5%. I tested all possible rates on several screens from different manufacturers with both RK3228 and RK3328. Both pre- and post-PLL locking are slighlty faster now. Signed-off-by:
Alex Bee <knaerzche@gmail.com> Signed-off-by:
Jonas Karlman <jonas@kwiboo.se> Link: https://lore.kernel.org/r/20230615171005.2251032-7-jonas@kwiboo.seSigned-off-by:
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Huicong Xu authored
Regular 8-bit and Deep Color video formats mainly differ in TMDS rate and not in pixel clock rate. When the hdmiphy clock is configured with the same pixel clock rate using clk_set_rate() the clock framework do not signal the hdmi phy driver to set_rate when switching between 8-bit and Deep Color. This result in pre/post pll not being re-configured when switching between regular 8-bit and Deep Color video formats. Fix this by calling set_rate in power_on to force pre pll re-configuration. Signed-off-by:
Huicong Xu <xhc@rock-chips.com> Signed-off-by:
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