- 01 Apr, 2014 40 commits
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Ben Widawsky authored
Reviewed-by:
Rodrigo Vivi <rodrigo.vivi@gmail.com> Signed-off-by:
Ben Widawsky <ben@bwidawsk.net> Signed-off-by:
Daniel Vetter <daniel.vetter@ffwll.ch>
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Ben Widawsky authored
We have a need for duplicated parsing of the RP_STATE_CAPS register (and the setting of the associated fields). To reuse some code, we can extract the function into a simple helper. This patch also addresses the fact that we missed doing this for gen8, something we should have done anyway. This could be two patches, one to extract, and one to add gen8, but it's trivial enough that I think one is fine. I will accept a request to split it. Please notice the fix addressed by v2 below. Valleyview is left untouched because it is different. v2: Logically rebased on top of commit dd0a1aa1 Author: Jeff McGee <jeff.mcgee@intel.com> Date: Tue Feb 4 11:32:31 2014 -0600 drm/i915: Restore rps/rc6 on reset Note with the above change the fix for gen8 is also handled (which was not the case in Jeff's original patch). Reviewed-by:
Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by:
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Ben Widawsky authored
Programming it outside of the rp0-rp1 range is considered a programming error. Since we do not know that the previous value would actually be in the range, program something we've read from the hardware, and therefore know will work. This is potentially an issue for platforms whose ranges are outside the norms given in the programming guide (ie. early silicon) v2: Use RP1 instead of RPn Reviewed-by:
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Ville Syrjälä authored
Split the post_disable hooks for DP to g4x and vlv variants. We'll need another variant soon, so this should make it look a bit cleaner. Signed-off-by:
Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by:
Jani Nikula <jani.nikula@intel.com> Signed-off-by:
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Ville Syrjälä authored
These were apparently meant to protect the SAREA which only has room for two pipes, but things clearly went a bit wonky when first the .update_plane() hooks were split up and then pipe C got introduced. The checks actually protecting the SAREA live in intel_crtc_update_sarea() these days, so the checks in the primary plane update hooks are just historical leftovers which are to be eliminated. Signed-off-by:
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Daniel Vetter authored
Progess according to the deprecation plan laid out in commit b30324ad Author: Daniel Vetter <daniel.vetter@ffwll.ch> Date: Wed Nov 13 22:11:25 2013 +0100 drm/i915: Deprecated UMS support and disable UMS for 3.16. Note that it has been over 5 years since the last UMS-supporting piece of userspace was released. Acked-by:
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Jani Nikula authored
There are no longer users of drm_i915_private_t. Drop the typedef. Good riddance. Signed-off-by:
Chris Wilson <chris@chris-wislon.co.uk> [danvet: Add the hunk in i915_cmd_parser.c here which had to be relocated to the how this was merged.] Signed-off-by:
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Damien Lespiau authored
The reg_read whitelist has a gen bitmask to code the gens we're allowing the register to be read on. Until now, it was a literal, but we can be a bit more expressive. To ease the review, a small test program: $ cat bit-range.c #include <stdio.h> #include <stdint.h> #define U32_C(x) x ## U #define GENMASK(h, l) (((U32_C(1) << ((h) - (l) + 1)) - 1) << (l)) #define GEN_RANGE(l, h) GENMASK(h, l) int main(int argc, char **argv) { printf("0x%08x\n", GEN_RANGE(1, 1)); printf("0x%08x\n", GEN_RANGE(1, 2)); printf("0x%08x\n", GEN_RANGE(4, 4)); printf("0x%08x\n", GEN_RANGE(4, 5)); printf("0x%08x\n", GEN_RANGE(1, 31)); printf("0x%08x\n", GEN_RANGE(4, 8)); return 0; } $ ./bit-range 0x00000002 0x00000006 0x00000010 0x00000030 0xfffffffe 0x000001f0 Signed-off-by:Damien Lespiau <damien.lespiau@intel.com> Reviewed-by:
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Deepak S authored
Let's change the i915_cur_delayinfo to i915_frequency_info to be in sync with new RPS naming convention. v2: Add "i915_frequency_info" as debugfs interface name (Ben) Signed-off-by:
Deepak S <deepak.s@linux.intel.com> Signed-off-by:
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Damien Lespiau authored
These defines are only used in intel_uncore.c. Signed-off-by:
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Damien Lespiau authored
That function isn't used outside this file anymore. Signed-off-by:
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Christoph Jaeger authored
DRM_DEBUG_KMS includes printing the function name. Signed-off-by:
Christoph Jaeger <christophjaeger@linux.com> Reviewed-by:
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Damien Lespiau authored
Those values are, global, only used in one function and already stored in mode_config.cursor_{width,height}. As a result, this initialization code has been moved from the crtc_init() function to the global modeset_init() one. I also renamed CURSOR_{WIDTH,HEIGHT} to MAX_CURSOR_{WIDTH,HEIGHT} to be more accurate about what these value really are. Cc: Sagar Kamble <sagar.a.kamble@intel.com> Cc: Chris Wilson <chris@chris-wilson.co.uk> Cc: Imre Deak <imre.deak@intel.com> Signed-off-by: -
Imre Deak authored
Besides D0 device state we need the proper power wells to be on on some platforms, so get the port power domain reference instead of an RPM reference. Signed-off-by:
Imre Deak <imre.deak@intel.com> Reviewed-by:
Antti Koskipää <antti.koskipaa@linux.intel.com> Signed-off-by:
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Imre Deak authored
Instead of reading out the CD clock rate from the HW at each modeset, do this only during driver init and resume and use the cached value during modeset. This moves things towards a state where the sw and hw side setup is separated. It's also needed for VLV RPM, where we don't put device into D0 state until modeset_global_resources is called and thus can't access any display/gfx registers. Signed-off-by:
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Chris Wilson authored
When trying to determine whether RPS is working as intended, more information is better. In particular, what interrupts are being generated and the various thresholds for generating them. Signed-off-by:
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Kenneth Graunke authored
Mesa needs to be able to write OACONTROL in order to expose the Observability Architecture's performance counters via OpenGL. Signed-off-by:
Kenneth Graunke <kenneth@whitecape.org> [danvet: Add comment that this is just a temporary work-around and that we need to check more things before we can allow OACONTROL writes for real everywhere.] [danvet 2: Squash in fixup to avoid a DRM_ERROR due to unsorted reg list, spotted by Jani.] Signed-off-by:
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Brad Volkin authored
v2: rebased OTC-Tracker: AXIA-4631 Change-Id: I6747457e1fe7494bd42787af51198fcba398ad78 Signed-off-by:
Brad Volkin <bradley.d.volkin@intel.com> Reviewed-by:
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Brad Volkin authored
So userspace can query the kernel for command parser support. v2: Add i915_cmd_parser_get_version(), history log, and kerneldoc OTC-Tracker: AXIA-4631 Change-Id: I58af650db9f6753c2dcac9c54ab432fd31db302f Signed-off-by:
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Brad Volkin authored
PIPE_CONTROL and MI_FLUSH_DW have bits that would write to the hardware status page. The driver stores request tracking info there, so don't let userspace overwrite it. v2: trailing comma fix, rebased Signed-off-by:
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Brad Volkin authored
Various commands that access memory have a bit to determine whether the graphics address specified in the command should use the GGTT or PPGTT for translation. These checks ensure that the bit indicates PPGTT translation. Most of these checks use the existing bit-checking infrastructure. The PIPE_CONTROL and MI_FLUSH_DW commands, however, are multi-function commands. The GGTT/PPGTT bit is only relevant for certain uses of the command. As such, this change also extends the bit-checking code to include a "condition" mask and offset. If the condition mask is non-zero then the parser only performs the bit check when the bits specified by the condition mask/offset are also non-zero. NOTE: At this point in the series PPGTT must be enabled for the parser to work correctly. If it's not enabled, userspace will not be setting the PPGTT bits the way the parser requires. VLV is the only platform where this is a problem, so at this point, we disable parsing for VLV. v2: whitespace and trailing commas fixes, rebased OTC-Tracker: AXIA-4631 Change-Id: I3f4c76b6734f1956ec47e698230f97d0998ff92b Signed-off-by:
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Brad Volkin authored
The driver leaves most interrupts masked during normal operation, so there would have to be additional work to enable userspace to safely request/receive an interrupt. v2: trailing commas, rebased Signed-off-by:
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Brad Volkin authored
MI_STORE_REGISTER_MEM, MI_LOAD_REGISTER_MEM, and MI_LOAD_REGISTER_IMM commands allow userspace access to registers. Only certain registers should be allowed for such access, so enable checking for those commands. Each ring gets its own register whitelist. MI_LOAD_REGISTER_REG on HSW also allows register access but is currently unused by userspace components. Leave it rejected. PIPE_CONTROL and MEDIA_VFE_STATE allow register access based on certain bits being set. Reject those as well. v2: trailing commas, rebased OTC-Tracker: AXIA-4631 Change-Id: Ie614a2f0eb2e5917de809e5a17957175d24cc44f Signed-off-by:
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Brad Volkin authored
These are used to implement scanline waits in the X server. v2: Use #defines instead of magic numbers Signed-off-by:
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Brad Volkin authored
These registers are currently used by mesa for blitting, transform feedback extensions, and performance monitoring extensions. v2: REG64 macro Signed-off-by:
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Brad Volkin authored
The Intel DDX uses these to implement scanline waits in the X server. Signed-off-by:
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Brad Volkin authored
The spec defines most of these commands as privileged. A few others, like the semaphore mbox command and some display commands, are also reserved for the driver's use. Subsequent patches relax some of these restrictions. v2: Rebased Signed-off-by:
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Brad Volkin authored
Add command tables defining irregular length commands for each ring. This requires a few new command opcode definitions. v2: Whitespace adjustment in command definitions, sparse fix for !F OTC-Tracker: AXIA-4631 Change-Id: I064bceb457e15f46928058352afe76d918c58ef5 Signed-off-by:
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Ben Widawsky authored
When PPGTT was disabled by default, the patch also prevented the user from overriding this behavior via module parameter. Being able to test this on arbitrary kernels is extremely beneficial to track down the remaining bugs. The patch that prevented this was: commit 93a25a9e Author: Daniel Vetter <daniel.vetter@ffwll.ch> Date: Thu Mar 6 09:40:43 2014 +0100 drm/i915: Disable full ppgtt by default By default PPGTT is set to -1. 0 means off, 1 means aliasing only, 2 means full, all other values are reserved. Signed-off-by:
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Ben Widawsky authored
This file contains all necessary defines, prototypes and typesdefs for manipulating GEN graphics address translation (this does not include the legacy AGP driver) Reiterating the comment in the header, "Please try to maintain the following order within this file unless it makes sense to do otherwise. From top to bottom: 1. typedefs 2. #defines, and macros 3. structure definitions 4. function prototypes Within each section, please try to order by generation in ascending order, from top to bottom (ie. GEN6 on the top, GEN8 on the bottom)." I've made some minor cleanups, and fixed a couple of typos while here - but there should be no functional changes. The purpose of the patch is to reduce clutter in our main header file, making room for new growth, and make documentation of our interfaces easier by splitting things out. With a little more work, like making i915_gtt a pointer, we could potentially completely isolate this header from i915_drv.h. At the moment however, I don't think it's worth the effort. Personally, I would have liked to put the PTE encoding functions in this file too, but I didn't want to rock the boat too much. A similar patch has been in use on my machine for some time. This exact patch though has only been compile tested. Signed-off-by:
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Daniel Vetter authored
Extract all this logic into a new helper function semaphore_wait_to_signaller_ring because: - The current code has way too much magic. - The current code doesn't look at bi16, which encodes VECS signallers on HSW. Those are just added after the fact, so can't be encoded in a neat formula. - The current logic can't blow up since it limits its value range sufficiently, but that's a bit too tricky to rely on in my opinion. Especially when we start to add bdw support. - I'm not a big fan of the explicit ring->semaphore_register list, but I think it's more robust to use the same mapping both when constructing the semaphore commands and when decoding them. - Finally add a FIXME comment about lack of broadwell support here, like in the earlier ipehr semaphore cmd detection function. Cc: Mika Kuoppala <mika.kuoppala@intel.com> Cc: Ben Widawsky <ben@bwidawsk.net> Cc: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by:
Mika Kuoppala <mika.kuoppala@intel.com> [danvet: Actually drop the untrue claim in the commit message Chris pointed out.] Signed-off-by:
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Daniel Vetter authored
Currently not an issue since we don't emit sempahores, but better not forget about those. As a little prep work extract the ipehr decoding for cleaner control flow. And apply a bit of polish. Cc: Ben Widawsky <ben@bwidawsk.net> Reviewed-by:
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Chris Wilson authored
The documentation calls this GFX_MODE bit "Flush TLB invalidate Mode". However, that is not a good name for an enable bit as it doesn't make it clear what is enabled. An even worse name is GFX_TLB_INVALIDATE_ALWAYS as enabling that bit actually prevents the TLB from being invalidated at every flush. This leads to great confusion when reading code and proposed patches. To get around this try to bake in what is enabled by setting the bit and call it GFX_TLB_INVALIDATE_EXPLICIT. Signed-off-by:
"Gupta, Sourab" <sourab.gupta@intel.com> Signed-off-by:
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Paulo Zanoni authored
Because gen6_gt_force_wake_{get,put} should already be responsible for getting/putting runtime PM. If we keep these calls, debugfs will not be testing the get/put calls of the forcewake functions. Signed-off-by:Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by:
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Paulo Zanoni authored
If runtime PM is enabled and we unset all modes, we will runtime suspend after __intel_set_mode() , then function intel_modeset_check_state() will try to read the HW state while it is suspended and trigger lots of WARNs because it shouldn't be reading registers. So on this patch we make intel_ddi_connector_get_hw_state() return false in case the power domain is disabled, and we also make intel_display_power_enabled() return false in case the device is suspended. Notice that we can't just use intel_display_power_enabled_sw() because while the driver is being initialized the power domain refcounts are not reflecting the real state of the hardware. Just for reference, I have previously published an alternate patch for this problem, called "drm/i915: get runtime PM at intel_set_mode". Testcase: igt/pm_pc8 Signed-off-by:
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Paulo Zanoni authored
At i915_display_info, don't call cursor_position() for a disabled CRTC, since the CRTC may be on a powered down pipe, and this will cause "Unclaimed register before interrupt" error messages. Testcase: igt/pm_pc8/debugfs-read Signed-off-by:
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Paulo Zanoni authored
Otherwise we may get some WARNs complaining that we're reading a register while we're suspended. Testcase: igt/pm_pc8/debugfs-read Signed-off-by:
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Paulo Zanoni authored
... at edp_have_panel_vdd. Just return false, saying we don't have the panel VDD since the device is suspended. We started getting WARNs about this problem since the patch that started checking if we're suspended while reading registers. Example backtrace provided by Paulo: [ 63.572201] [drm:hsw_enable_pc8] Enabling package C8+ [ 63.581831] [drm:i915_runtime_suspend] Device suspended [ 63.664798] ------------[ cut here ]------------ [ 63.664824] WARNING: CPU: 3 PID: 828 at drivers/gpu/drm/i915/intel_uncore.c:47 assert_device_not_suspended.isra.7+0x32/0x40 [i915]() [ 63.664826] Device suspended [ 63.664828] Modules linked in: ccm fuse ip6table_filter ip6_tables ebtable_nat ebtables arc4 ath9k_htc ath9k_common ath9k_hw mac80211 ath cfg80211 iTCO_wdt iTCO_vendor_support x86_pkg_temp_thermal coretemp microcode i2c_i801 e1000e pcspkr serio_raw lpc_ich ptp pps_core mei_me mei mfd_core dm_crypt i915 crc32_pclmul crc32c_intel ghash_clmulni_intel i2c_algo_bit drm_kms_helper drm video [ 63.664867] CPU: 3 PID: 828 Comm: kworker/3:3 Not tainted 3.14.0+ #153 [ 63.664869] Hardware name: Intel Corporation Shark Bay Client platform/WhiteTip Mountain 1, BIOS HSWLPTU1.86C.0133.R00.1309172123 09/17/2013 [ 63.664887] Workqueue: events edp_panel_vdd_work [i915] [ 63.664889] 0000000000000009 ffff88009d745c28 ffffffff8167ec6f ffff88009d745c70 [ 63.664895] ffff88009d745c60 ffffffff8106c8ed ffff880036278000 00000000000c7204 [ 63.664900] ffff88014f2d3040 ffff880036278070 0000000000000001 ffff88009d745cc0 [ 63.664905] Call Trace: [ 63.664911] [<ffffffff8167ec6f>] dump_stack+0x4d/0x66 [ 63.664916] [<ffffffff8106c8ed>] warn_slowpath_common+0x7d/0xa0 [ 63.664920] [<ffffffff8106c95c>] warn_slowpath_fmt+0x4c/0x50 [ 63.664926] [<ffffffff810bd6be>] ? mark_held_locks+0xae/0x130 [ 63.664941] [<ffffffffa00d80d2>] assert_device_not_suspended.isra.7+0x32/0x40 [i915] [ 63.664956] [<ffffffffa00d99d2>] gen6_read32+0x32/0x120 [i915] [ 63.664969] [<ffffffffa00d99a0>] ? gen6_read8+0x120/0x120 [i915] [ 63.664985] [<ffffffffa0106f8f>] edp_have_panel_vdd+0x3f/0x50 [i915] [ 63.665000] [<ffffffffa01074e8>] edp_panel_vdd_off_sync+0x58/0x1c0 [i915] [ 63.665004] [<ffffffff8108a06c>] ? process_one_work+0x18c/0x560 [ 63.665018] [<ffffffffa0107684>] edp_panel_vdd_work+0x34/0x50 [i915] [ 63.665022] [<ffffffff8108a0d7>] process_one_work+0x1f7/0x560 [ 63.665026] [<ffffffff8108a06c>] ? process_one_work+0x18c/0x560 [ 63.665031] [<ffffffff8108ae2b>] worker_thread+0x11b/0x3a0 [ 63.665035] [<ffffffff8108ad10>] ? manage_workers.isra.21+0x2a0/0x2a0 [ 63.665039] [<ffffffff810916fc>] kthread+0xfc/0x120 [ 63.665043] [<ffffffff81091600>] ? kthread_create_on_node+0x230/0x230 [ 63.665048] [<ffffffff8169082c>] ret_from_fork+0x7c/0xb0 [ 63.665052] [<ffffffff81091600>] ? kthread_create_on_node+0x230/0x230 [ 63.665054] ---[ end trace 1250bcc890af9999 ]--- [ 63.665060] [drm:edp_panel_vdd_off_sync] Turning eDP VDD off [ 63.665061] ------------[ cut here ]------------ Testcase: igt/pm_pc8 Signed-off-by:
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Paulo Zanoni authored
To avoid WARNs when we call it. Testcase: igt/pm_pc8/reg-read-ioctl Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=75693Signed-off-by:
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Paulo Zanoni authored
So far force_wake_timer was only used by gen6_gt_force_wake_put. Since we always had balanced gen6_gt_force_wake_get/put calls, we could guarantee balanced calls to intel_runtime_pm_get/put. Commit 8232644c, "drm/i915: Convert the forcewake worker into a timer func" started scheduling the force_wake_timer at gen6_read, which resulted in an unbalanced runtime_pm refcount. So this commit just reverts to the old behavior until we can find a proper way to used delayed force_wake from the register read/write macros without leaving the runtime_pm refcounts unbalanced and without runtime suspending the driver while forcewake is active. Testcase: igt/pm_pc8/rte Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=76544Signed-off-by:
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