- 18 Jul, 2024 1 commit
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Conor Dooley authored
When Maxime originally added the BH2228FV to the spidev driver, he spelt it incorrectly - the d should have been a b. That spelling was then propagated to the binding when written by Krzysztof. Add a new, correctly spelt compatible and advise against using the incorrectly spelling. Fixes: 025aea27 ("dt-bindings: trivial-devices: document SPI dev compatibles") Signed-off-by:
Conor Dooley <conor.dooley@microchip.com> Acked-by:
Maxime Ripard <mripard@kernel.org> Link: https://patch.msgid.link/20240717-exuberant-enlighten-f890fabcd247@spudSigned-off-by:
Mark Brown <broonie@kernel.org>
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- 15 Jul, 2024 6 commits
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Steve Wilkins authored
The current implementation only supports a word size of 8 bits, which limits the devices it can be used with. Add support for any word size between 1 and 32 bits, as supported by the hardware. Signed-off-by:
Steve Wilkins <steve.wilkins@raymarine.com> Signed-off-by:
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Steve Wilkins authored
While transmitting with rx_len == 0, the RX FIFO is not going to be emptied in the interrupt handler. A subsequent transfer could then read crap from the previous transfer out of the RX FIFO into the start RX buffer. The core provides a register that will empty the RX and TX FIFOs, so do that before each transfer. Fixes: 9ac8d176 ("spi: add support for microchip fpga spi controllers") Signed-off-by:
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Steve Wilkins authored
mchp_corespi_init() reads the CONTROL register, sets the master and motorola bits, but doesn't write the value back to the register. The function also doesn't ensure the controller is disabled at the start, which may present a problem if the controller was used by an earlier boot stage as some settings (including the mode) can only be modified while the controller is disabled. Fixes: 9ac8d176 ("spi: add support for microchip fpga spi controllers") Signed-off-by:
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Steve Wilkins authored
Setting up many of the registers for a new SPI transfer involves unconditionally disabling the SPI controller, writing the register value and re-enabling the controller. This is being done for registers even when the value is unchanged and is also done for registers that don't require the controller to be disabled for the change to take effect. Make an effort to detect changes to the register values, and only disables the controller if the new register value is different and disabling the controller is required. This stops the controller being repeated disabled and the bus going tristate before every transfer. Fixes: 9ac8d176 ("spi: add support for microchip fpga spi controllers") Signed-off-by:
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Steve Wilkins authored
Setting up many of the registers for a new SPI transfer requires the SPI controller to be disabled after set_cs() has been called to assert the chip select line. However, disabling the controller results in the SCLK and MOSI output pins being tristate, which can cause clock transitions to be seen by a slave device whilst SS is active. To fix this, the CS is only set to inactive inline, whilst setting it active is deferred until all registers are set up and the any controller disables have been completed. Fixes: 9ac8d176 ("spi: add support for microchip fpga spi controllers") Signed-off-by:
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Naga Sureshkumar Relli authored
It is possible for the TXDONE interrupt be raised if the tx FIFO becomes temporarily empty while transmitting, resulting in recursive calls to mchp_corespi_write_fifo() and therefore a garbage message might be transmitted depending on when the interrupt is triggered. Moving all of the tx FIFO writes out of the TXDONE portion of the interrupt handler avoids this problem. Most of rest of the TXDONE portion of the handler is problematic too. Only reading the rx FIFO (and finalising the transfer) when the TXDONE interrupt is raised can cause the transfer to stall, if the final bytes of rx data are not available in the rx FIFO when the final TXDONE interrupt is raised. The transfer should be finalised regardless of which interrupt is raised, provided that all tx data has been set and all rx data received. The first issue was encountered "in the wild", the second is theoretical. Fixes: 9ac8d176 ("spi: add support for microchip fpga spi controllers") Signed-off-by:
Naga Sureshkumar Relli <nagasuresh.relli@microchip.com> Signed-off-by:
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- 11 Jul, 2024 1 commit
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Nicolas Ferre authored
Add compatible string for sama7d65. Like sam9x60 and sam9x7, it requires to bind to "atmel,at91rm9200-spi". Group these three under the same enum, sorted alphanumerically, and remove previously added item. Signed-off-by:
Nicolas Ferre <nicolas.ferre@microchip.com> Acked-by:
Rob Herring (Arm) <robh@kernel.org> Link: https://patch.msgid.link/20240711165402.373634-1-nicolas.ferre@microchip.comSigned-off-by:
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- 08 Jul, 2024 5 commits
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Johannes Thumshirn authored
Add a driver for the QiHeng Electronics ch341a USB-to-SPI adapter. This driver is loosely based on the ch341a module from the flashrom project. Signed-off-by:
Johannes Thumshirn <jth@kernel.org> Link: https://patch.msgid.link/20240708-spi-ch341a-v3-1-cf7f9b2c1e31@kernel.orgSigned-off-by:
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Frank Li authored
Add compatible string 'fsl,lx2160a-dspi' and allow fall back to 'fsl,ls2085a-dspi'. Fix below CHECK_DTBS warning. arch/arm64/boot/dts/freescale/fsl-lx2160a-bluebox3.dtb: spi@2100000: compatible: 'oneOf' conditional failed, one must be fixed: ['fsl,lx2160a-dspi', 'fsl,ls2085a-dspi'] is too long Signed-off-by:Frank Li <Frank.Li@nxp.com> Link: https://patch.msgid.link/20240703165931.2325807-2-Frank.Li@nxp.comSigned-off-by:
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Frank Li authored
Add dmas and dma-names properties because dspi support dma transfer. Fix below warnings: arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28-var1.dtb: spi@2120000: Unevaluated properties are not allowed ('dma-names', 'dmas', 'little-endian' were unexpected) from schema $id: http://devicetree.org/schemas/spi/fsl,dspi.yaml#Reviewed-by:Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by:
Vladimir Oltean <olteanv@gmail.com> Link: https://patch.msgid.link/20240703165931.2325807-1-Frank.Li@nxp.comSigned-off-by:
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Li zeming authored
status is assigned first, so it does not need to initialize the assignment. Signed-off-by:
Li zeming <zeming@nfschina.com> Link: https://patch.msgid.link/20240708041411.14424-1-zeming@nfschina.comSigned-off-by:
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Li zeming authored
rc is assigned first, so it does not need to initialize the assignment. Signed-off-by:
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- 05 Jul, 2024 4 commits
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Nuno Sa authored
Just cosmetics. No functional change intended. While at it, removed a couple of redundant else if() statements. Signed-off-by:
Nuno Sa <nuno.sa@analog.com> Link: https://patch.msgid.link/20240705-dev-spi-xcomm-gpiochip-v2-4-b10842fc9636@analog.comSigned-off-by:
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Nuno Sa authored
i2c_get_clientdata() is not being called anywhere so that we do not need to set clientdata. Signed-off-by:
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Nuno Sa authored
Use devm_spi_alloc_host() so that there's no need to call spi_controller_put() in the error path. Signed-off-by:
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Michael Hennerich authored
The hardware can expose one pin as a GPO. Hence, register a simple gpiochip to support it. Signed-off-by:
Michael Hennerich <michael.hennerich@analog.com> Co-developed-by:
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- 01 Jul, 2024 3 commits
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Kanak Shilledar authored
updated compatible property to include "thead,th1520-spi" for the TH1520 SoC SPI Controller. Signed-off-by:
Kanak Shilledar <kanakshilledar@gmail.com> Acked-by:
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Frank Li authored
Convert dt-binding spi-fsl-dspi.txt to yaml format. Use part Vladimir Oltean's work at of https://lore.kernel.org/linux-spi/20221111224651.577729-1-vladimir.oltean@nxp.com/ Additional changes during convert: - compatible string "fsl,ls1028a-dspi" can be followed by fsl,ls1021a-v1.0-dspi. - Change "dspi0@4002c000" to "spi@4002c000" in example. - Reorder properties in example. - Use GIC include in example. - Deprecated fsl,spi-cs-sck-delay and fsl,spi-sck-cs-delay by use common SPI property. - Use compatible string 'jedec,spi-nor' in example. - Split peripheral part to fsl,dspi-peripheral-props.yaml. - Remove 'interrupts' and 'pinctrl' from required list. - Update 'bus-num' description. - Update 'spi-num-chipselects' description by add "cs-gpios don't count against this number". - Remove 'big-endian' description. Co-developed-by:
Kuldeep Singh <kuldeep.singh@nxp.com> Signed-off-by:
Vladimir Oltean <vladimir.oltean@nxp.com> Signed-off-by:
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Frank Li authored
Use SPI common DT binding properties 'spi-cs-setup-delay-ns' and 'spi-cs-hold-delay-ns'. If these properties do not exist, fall back to legacy 'fsl,spi-cs-sck-delay' and 'fsl,spi-sck-cs-delay'. Signed-off-by:
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- 27 Jun, 2024 1 commit
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David Lechner authored
platform_get_drvdata() is never called in the AXI SPI Engine driver, so platform_set_drvdata() is not needed. Remove it. This also lets us avoid the final error check in the probe function. Signed-off-by:
David Lechner <dlechner@baylibre.com> Reviewed-by:
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- 25 Jun, 2024 5 commits
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Fabio Estevam authored
After coverting to SYSTEM_SLEEP_PM_OPS, it is necessary to pass pm_ptr() to the PM operations. Fix it accordingly. Fixes: 6765e859 ("spi: spi-fsl-lpspi: Switch to SYSTEM_SLEEP_PM_OPS()") Signed-off-by:
Fabio Estevam <festevam@denx.de> Link: https://patch.msgid.link/20240625183919.368770-2-festevam@gmail.comSigned-off-by:
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Fabio Estevam authored
After coverting to RUNTIME_PM_OPS/SYSTEM_SLEEP_PM_OPS, it is necessary to pass pm_ptr() to the PM operations. Fix it accordingly. Fixes: a93f089c ("spi: spi-imx: Switch to RUNTIME_PM_OPS/SYSTEM_SLEEP_PM_OPS()") Signed-off-by:
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Mark Brown authored
Merge series from David Lechner <dlechner@baylibre.com>: In the IIO subsystem, we are finding that it is common to call spi_optimize_message() during driver probe since the SPI message doesn't change for the lifetime of the driver. This patch adds a devm_spi_optimize_message() helper to simplify this common pattern.
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Fabio Estevam authored
Replace SET_SYSTEM_SLEEP_PM_OPS with its modern SYSTEM_SLEEP_PM_OPS() alternative. The combined usage of pm_ptr() and SYSTEM_SLEEP_PM_OPS() allows the compiler to evaluate if the runtime suspend/resume() functions are used at build time or are simply dead code. This allows removing the __maybe_unused notation from the runtime suspend/resume() functions. Signed-off-by:
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Fabio Estevam authored
Replace SET_RUNTIME_PM_OPS()/SET SYSTEM_SLEEP_PM_OPS() with their modern RUNTIME_PM_OPS() and SYSTEM_SLEEP_PM_OPS() alternatives. The combined usage of pm_ptr() and RUNTIME_PM_OPS/SYSTEM_SLEEP_PM_OPS() allows the compiler to evaluate if the runtime suspend/resume() functions are used at build time or are simply dead code. This allows removing the __maybe_unused notation from the runtime suspend/resume() functions. Signed-off-by:
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- 24 Jun, 2024 1 commit
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David Lechner authored
devm_spi_optimize_message() is a public function and needs EXPORT_SYMBOL_GPL. Reported-by:
Jonathan Cameron <jic23@kernel.org> Closes: https://lore.kernel.org/linux-iio/20240624204424.6a91a5e4@jic23-huawei/ Fixes: d4a0055f ("spi: add devm_spi_optimize_message() helper") Signed-off-by:
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- 23 Jun, 2024 1 commit
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Mark Brown authored
Merge series from David Lechner <dlechner@baylibre.com>: In the IIO subsystem, we are finding that it is common to call spi_optimize_message() during driver probe since the SPI message doesn't change for the lifetime of the driver. This patch adds a devm_spi_optimize_message() helper to simplify this common pattern.
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- 22 Jun, 2024 2 commits
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David Lechner authored
This adds a new helper function devm_spi_optimize_message() that automatically registers spi_unoptimize_message() to be called when the device is removed. Signed-off-by:
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David Lechner authored
A few SPI devm_* helpers were missing from the devres documentation. This patch adds them. Signed-off-by:
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- 21 Jun, 2024 1 commit
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Uwe Kleine-König authored
While in commit 2dd33f9c ("spi: imx: support DMA for imx35") it was claimed that DMA works on i.MX25, i.MX31 and i.MX35 the respective device trees don't add DMA channels. The Reference manuals of i.MX31 and i.MX25 also don't mention the CSPI core being DMA capable. (I didn't check the others.) Since commit e267a5b3 ("spi: spi-imx: Use dev_err_probe for failed DMA channel requests") this results in an error message spi_imx 43fa4000.spi: error -ENODEV: can't get the TX DMA channel! during boot. However that isn't fatal and the driver gets loaded just fine, just without using DMA. Signed-off-by:
Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Link: https://patch.msgid.link/20240508095610.2146640-2-u.kleine-koenig@pengutronix.deSigned-off-by:
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- 20 Jun, 2024 3 commits
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Simon Trimmer authored
OEMs can connect a number of types of speakers to the sidecar cs35l56 amplifiers and a different speaker requires a different firmware configuration. When the cs42l43 ACPI includes a property indicating a particular type of speaker has been installed this should be passed to the cs35l56 driver instances as a device property. Signed-off-by:
Simon Trimmer <simont@opensource.cirrus.com> Signed-off-by:
Charles Keepax <ckeepax@opensource.cirrus.com> Link: https://patch.msgid.link/20240619121703.3411989-2-ckeepax@opensource.cirrus.comSigned-off-by:
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Charles Keepax authored
Refactor accessing the SDCA extension properties to make it easier to access multiple properties to assist with future features. Return the node itself and allow the caller to read the actual properties. Signed-off-by:
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Mark Brown authored
We need the fixes to apply new changes to the Cirrus drivers.
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- 19 Jun, 2024 2 commits
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Marc Kleine-Budde authored
The patch 15a6af94 ("spi: Increase imx51 ecspi burst length based on transfer length") increased the burst length calculation in mx51_ecspi_prepare_transfer() to be based on the transfer length. This breaks HW CS + SPI_CS_WORD support which was added in 6e95b23a ("spi: imx: Implement support for CS_WORD") and transfers with bits-per-word != 8, 16, 32. SPI_CS_WORD means the CS should be toggled after each word. The implementation in the imx-spi driver relies on the fact that the HW CS is toggled automatically by the controller after each burst length number of bits. Setting the burst length to the number of bits of the _whole_ message breaks this use case. Further the patch 15a6af94 ("spi: Increase imx51 ecspi burst length based on transfer length") claims to optimize the transfers. But even without this patch, on modern spi-imx controllers with "dynamic_burst = true" (imx51, imx6 and newer), the transfers are already optimized, i.e. the burst length is dynamically adjusted in spi_imx_push() to avoid the pause between the SPI bursts. This has been confirmed by a scope measurement on an imx6d. Subsequent Patches tried to fix these and other problems: - 5f66db08 ("spi: imx: Take in account bits per word instead of assuming 8-bits") - e9b220ae ("spi: spi-imx: correctly configure burst length when using dma") - c712c05e ("spi: imx: fix the burst length at DMA mode and CPU mode") - cf6d79a0 ("spi: spi-imx: fix off-by-one in mx51 CPU mode burst length") but the HW CS + SPI_CS_WORD use case is still broken. To fix the problems revert the burst size calculation in mx51_ecspi_prepare_transfer() back to the original form, before 15a6af94 ("spi: Increase imx51 ecspi burst length based on transfer length") was applied. Cc: Stefan Moring <stefan.moring@technolution.nl> Cc: Stefan Bigler <linux@bigler.io> Cc: Clark Wang <xiaoning.wang@nxp.com> Cc: Carlos Song <carlos.song@nxp.com> Cc: Sebastian Reichel <sre@kernel.org> Cc: Thorsten Scherer <T.Scherer@eckelmann.de> Fixes: 15a6af94 ("spi: Increase imx51 ecspi burst length based on transfer length") Fixes: 5f66db08 ("spi: imx: Take in account bits per word instead of assuming 8-bits") Fixes: e9b220ae ("spi: spi-imx: correctly configure burst length when using dma") Fixes: c712c05e ("spi: imx: fix the burst length at DMA mode and CPU mode") Fixes: cf6d79a0 ("spi: spi-imx: fix off-by-one in mx51 CPU mode burst length") Link: https://lore.kernel.org/all/20240618-oxpecker-of-ideal-mastery-db59f8-mkl@pengutronix.deSigned-off-by:
Marc Kleine-Budde <mkl@pengutronix.de> Tested-by:
Thorsten Scherer <t.scherer@eckelmann.de> Link: https://msgid.link/r/20240618-spi-imx-fix-bustlength-v1-1-2053dd5fdf87@pengutronix.deSigned-off-by:
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Amit Kumar Mahapatra authored
When spi-cadence is configured as a slave, it requires the SPI refclk to detect the synchronization start condition while communicating with the master. However, the spi-cadence driver never enables the SPI refclk in slave mode, causing the refclk to remain disabled if the "clk_ignore_unused" kernel parameter is not passed through bootargs. As a result, the slave cannot detect data sent by the master, leading to communication failure. Update driver to enable the SPI refclk in both master and slave configurations. Fixes: b1b90514 ("spi: spi-cadence: Add support for Slave mode") Signed-off-by:
Amit Kumar Mahapatra <amit.kumar-mahapatra@amd.com> Link: https://msgid.link/r/20240617153837.29861-1-amit.kumar-mahapatra@amd.comSigned-off-by:
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- 18 Jun, 2024 4 commits
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Amit Kumar Mahapatra authored
While adding a SPI device, the SPI core ensures that multiple logical CS doesn't map to the same physical CS. For example, spi->chip_select[0] != spi->chip_select[1] and so forth. However, unlike the SPI master, the SPI slave doesn't have the list of chip selects, this leads to probe failure when the SPI controller is configured as slave. Update the __spi_add_device() function to perform this check only if the SPI controller is configured as master. Fixes: 4d8ff6b0 ("spi: Add multi-cs memories support in SPI core") Signed-off-by:
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Charles Keepax authored
Refactor accessing the SDCA extension properties to make it easier to access multiple properties to assist with future features. Return the node itself and allow the caller to read the actual properties. Signed-off-by:
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Patrice Chotard authored
Add OCTAL mode support. Issue detected using "--octal" spidev_test's option. Signed-off-by:
Patrice Chotard <patrice.chotard@foss.st.com> Link: https://msgid.link/r/20240618132951.2743935-4-patrice.chotard@foss.st.comSigned-off-by:
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Patrice Chotard authored
In case usage of OCTAL mode, buswidth parameter can take the value 8. As return value of stm32_qspi_get_mode() is used to configure fields of CCR registers that are 2 bits only (fields IMODE, ADMODE, ADSIZE, DMODE), clamp return value of stm32_qspi_get_mode() to 4. Fixes: a557fca6 ("spi: stm32_qspi: Add transfer_one_message() spi callback") Cc: stable@vger.kernel.org Signed-off-by:
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