- 14 Jan, 2021 40 commits
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chen gong authored
The address of the GOLDEN_TSC_COUNT_UPPER/GOLDEN_TSC_COUNT_LOWER for Vnagogh are different from the others. The offset of the GOLDEN_TSC_COUNT_UPPER for Vangogh is 0x0025 by calculation. The offset of the GOLDEN_TSC_COUNT_LOWER for Vangogh is 0x0026 by calculation. Signed-off-by:
chen gong <curry.gong@amd.com> Acked-by:
Evan Quan <evan.quan@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Huang Rui authored
This patch is to implement the processor fine grain feature for vangogh. It's similar with gfx clock, the only difference is below: echo "p core_id level value" > pp_od_clk_voltage 1. "p" - set the cclk (processor) frequency 2. "core_id" - 0/1/2/3, represents which cpu core you want to select 2. "level" - 0 or 1, "0" represents the min value, "1" represents the max value 3. "value" - the target value of cclk frequency, it should be limited in the safe range v2: fix some missing changes as Evan's suggestion. v3: add version check and fix the restore. Signed-off-by:
Huang Rui <ray.huang@amd.com> Reviewed-by:
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Huang Rui authored
The core processor clocks will be stored in smu metric table, then we add this runtime information into amdgpu_pm_info interface. Signed-off-by:
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Xiaojian Du authored
This patch is to add the workload map for vangogh. Signed-off-by:
Xiaojian Du <Xiaojian.Du@amd.com> Reviewed-by:
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Xiaojian Du authored
This patch is to fix one superfluous error for renoir. Renoir supports 5 kinds of power profile mode: "FULL SCREEN 3D", "VIDEO", "VR", "COMPUTE" and "CUSTOM". After loading amdgpu driver, the driver will set "BOOTUP_DEFAULT" mode to APU, and it will get one superfluouserror error, which is saying "Unsupported power profile mode 0 on RENOIR", but it will not make any other harmful events, so fix this error. Signed-off-by:
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Xiaojian Du authored
This patch is to support the function to change power profile mode for vangogh. Vangogh supports 5 kinds of power profile mode: "FULL SCREEN 3D", "VIDEO", "VR", "COMPUTE" and "CUSTOM". Signed-off-by:
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Jinzhou Su authored
Add Enable gfxoff for Vangogh during smu_post_init. System will not enter GfxOff without allow message. Signed-off-by:
Jinzhou Su <Jinzhou.Su@amd.com> Reviewed-by:
Lijo Lazar <lijo.lazar@amd.com> Acked-by:
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Jinzhou Su authored
Steps to enter gfxoff mode on Vangogh 1. Send EnableGfxOff message to SMU 2. Send AllowGfxOff message to SMU Signed-off-by:
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Bhawanpreet Lakha authored
[Why] during idle optimizations we acquire the dc_lock, this lock is also acquired during gpu_reset so we end up hanging the system due to a deadlock [How] If we are in gpu reset: - disable idle optimizations and skip calls to the dc function v2: skip idle optimizations calls v3: add guard for DCN Fixes: 71338cb4 ("drm/amd/display: enable idle optimizations for linux (MALL stutter)") Signed-off-by:
Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Reviewed-by:
Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by:
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Huang Rui authored
0 should be right driver return value, 0x1 is the right firmware return value. So switch to 0 at last. Signed-off-by:
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Huang Rui authored
PCIE MMIO bar needs to be restored firstly after the reset event triggers. So it's unable to access the registers to wait for response from SMU. Becasue the value of mmMP1_SMN_C2PMSG_90 is invalid at that moment. Signed-off-by:
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Alex Deucher authored
Enable GPU reset when we encounter a hang. Acked-by:
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Alex Deucher authored
We need to save and restore PCI config space. Signed-off-by:
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Alex Deucher authored
Vangogh will use mode2 reset, so plumb it through the nv soc driver. Acked-by:
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Alex Deucher authored
GPU reset is handled via SMU similar to previous APUs. Acked-by:
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Jack Zhang authored
[Why] When host trigger a whole gpu reset, guest will keep waiting till host finish reset. But there's a work queue in guest exchanging data between vf&pf which need to access frame buffer. During whole gpu reset, frame buffer is not accessable, and this causes the call trace. [How] After vf get reset notification from pf, stop data exchange. Signed-off-by:
Jingwen Chen <Jingwen.Chen2@amd.com> Signed-off-by:
Jack Zhang <Jack.Zhang1@amd.com> Reviewed-by:
Monk Liu <monk.liu@amd.com> Signed-off-by:
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Huang Rui authored
VHG based APU will support feature mask checking. Signed-off-by:
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Huang Rui authored
VanGogh supports feature mask checking which exposed by smu firmware. It has to initial at first, otherwise, all SMU_FEATURE_xxx masks are invalid. Signed-off-by:
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Huang Rui authored
The get_allowed_feature_mask is superfluous on vangogh. Signed-off-by:
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Huang Rui authored
The user prefers to know the real response value from C2PMSG 90 register which is written by firmware not -EIO. v2: return C2PMSG 90 value Signed-off-by:
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Huang Rui authored
VCN/JPEG PG won't be a feature mask bit which exposed by vangogh smu firmware. So remove it. Signed-off-by:
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Jeremy Cline authored
KASAN reported a slab-out-of-bounds read of size 1 in kdf_create_vcrat_image_cpu(). This occurs when, for example, when on an x86_64 with a single NUMA node because kfd_fill_iolink_info_for_cpu() is a no-op, but afterwards the sub_type_hdr->length, which is out-of-bounds, is read and multiplied by entries. Fortunately, entries is 0 in this case so the overall crat_table->length is still correct. Check if there were any entries before de-referencing sub_type_hdr which may be pointing to out-of-bounds memory. Fixes: b7b6c385 ("drm/amdkfd: Calculate CPU VCRAT size dynamically (v2)") Suggested-by:
Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by:
Jeremy Cline <jcline@redhat.com> Reviewed-by:
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Emily.Deng authored
For multiple VF, after engine hang,as host driver will first encounter FLR, so has no meanning to set compute to 60s. v2: Refine the patch and comment Signed-off-by:
Emily.Deng <Emily.Deng@amd.com> Acked-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
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Rodrigo Siqueira authored
commit a861736d ("drm/amd/display: Fixed Intermittent blue screen on OLED panel") causes power regression for many users. It seems that this change causes the MCLK to get forced high; this creates a regression for many users since their devices were not able to drop to a low state after this change. For this reason, this reverts commit a861736d. Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1407 Cc: Aurabindo Pillai <aurabindo.pillai@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: Harry Wentland <harry.wentland@amd.com> Cc: Naveed Ashfaq <Naveed.Ashfaq@amd.com> Cc: Hersen Wu <hersenxs.wu@amd.com> Cc: Roman Li <roman.li@amd.com> Acked-by:
Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by:
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Charlene Liu authored
[why] driver has sent PMFW VBIOSSMC_MSG_SetDisplayIdleOptimizations while SMU still processing a previous VBIOSSMC_MSG_SetHardMinDcfclkByFreq message. [how] same as RN, change the time out to2s. Tested-by:
Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by:
Charlene Liu <Charlene.Liu@amd.com> Reviewed-by:
Chris Park <Chris.Park@amd.com> Acked-by:
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Li, Roman authored
[Why] The initial purpose of dcn10 pipe split is to support some high bandwidth mode which requires dispclk greater than max dispclk. By initial bring up power measurement data, it showed power consumption is less with pipe split for dcn block. This could be reason for enable pipe split by default. By battery life measurement of some Chromebooks, result shows battery life is longer with pipe split disabled. [How] Disable pipe split by default. Pipe split could be still enabled when required dispclk is greater than max dispclk. Tested-by:
Hersen Wu <hersenxs.wu@amd.com> Signed-off-by:
Roman Li <Roman.Li@amd.com> Reviewed-by:
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Aric Cyr authored
Signed-off-by:
Aric Cyr <aric.cyr@amd.com> Acked-by:
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Nikola Cornij authored
[why] Required for DSC MST Tested-by:
Nikola Cornij <nikola.cornij@amd.com> Reviewed-by:
Zhan Liu <Zhan.Liu@amd.com> Acked-by:
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Bhawanpreet Lakha authored
- Reverts "drm/amd/display: Revert HUBP blank behaviour for now" - Hubp blank will fail if the pipe is locked (this is the case on linux), so add a check to make sure pipe isn't locked, if it is then defer the blank to post_unlock. Tested-by:
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Wesley Chalmers authored
[WHY] DCN30 has a bug where blanking HUBP blocks pstate allow unless HUBP_DISABLE is toggled afterwards. [HOW] Create a HW sequence for blanking HUBP. 1. Wait for enter VBLANK 2. Set HUBP_BLANK 3. Make sure HUBP_IN_BLANK = 1 4. Toggle HUBP_DISABLE on and off to perform soft reset All existing calls to hubp->funcs->set_blank should be replaced with this new sequence. In wait_for_mpcc_disconnect, only blank the pipe being disconnected, and leave all other pipes unmodified. Tested-by:
Wesley Chalmers <Wesley.Chalmers@amd.com> Reviewed-by:
Jun Lei <Jun.Lei@amd.com> Acked-by:
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Jacky Liao authored
[Why] A call to BREAK_TO_DEBUGGER is triggered when powering down memory [How] Remove the check for GAMCOR_MEM_PWR_STATE when powering off the memory Tested-by:
Jacky Liao <ziyu.liao@amd.com> Reviewed-by:
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Raymond Yang authored
[Why] Seamless boot stream has hw resource assigned, already. 'add' is actually rebuild the assignment. [How] Swap seamless boot stream to pipe 0 (if needed) to ensure pipe_ctx matches Tested-by:
Raymond Yang <rayyang@amd.com> Reviewed-by:
Martin Leung <Martin.Leung@amd.com> Acked-by:
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Jun Lei authored
[why] When OS reboots, and panel is turned off, T12 may not be maintained. T12 is defined as the interval between VDDC off (occurs at shutdown) and the next VDDC on (occurs when eDP is POST-ed) [how] DC already tracks panel power off time. Add a DC interface which DM can call during shutdown. Ideally this should be as late as possible during the shutdown sequence so the extra delay is minimal. Tested-by:
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Mike Hsieh authored
Tested-by:
Mike Hsieh <chun-wei.hsieh@amd.com> Reviewed-by:
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Yu-ting Shen authored
[Why] 1. the corrected timing to write DPCD 300h AMD signature is before link training. 2. and VBIOS will writes correctted AMD signature by after AGESA 1.0.0, so driver doesn't need to write DPCD 300h again to switch config. 3. there are some OLED panel will clean backlight level to 0 once receive DPCD 300h, so we will see flicker issue at that time. [How] read DPCD 300h signature before write it to avoid reprogram again, if AMD signature was writed corrected by VBIOS, driver will not reprogram it again. Tested-by:
Yu-ting Shen <Yu-ting.Shen@amd.com> Reviewed-by:
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Chiawen Huang authored
[Why] When switching single pipe to split pipe, the bandwidth check is just for first pipe. The 2nd pipe with abnormal(or zero) dpp clock when pipe ready and unlock leads the garbage on display. [How] Removed external increasing dpp clock check, the internal function already loops all of pipes to check whether update dpp clock. Tested-by:
Chiawen Huang <chiawen.huang@amd.com> Reviewed-by:
Tony Cheng <Tony.Cheng@amd.com> Acked-by:
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Wesley Chalmers authored
[WHY] We want to make enabling test pattern a part of the stream update code path. This change is the first step towards that goal. Tested-by:
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Wesley Chalmers authored
[WHY] DCN10 uses plane visibility to determine when to unblank HUBP; there is no reason DCN20+ should not do the same. [HOW] In addition to changing the check in HWSEQ, we must change is_pipe_tree_visible so that it checks ODM pipe topologies as well as MPC. Since we're now checking both ODM and MPC topologies, the helper function names have been changed to reference "parent" and "child" instead of "top" and "bottom". Tested-by:
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Wesley Chalmers authored
[WHY] Shift/mask for HUBP_IN_BLANK is currently missing. Tested-by:
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Lewis Huang authored
[Why] Driver apply the monitor patch into global debug flag. When apply monitor patch, fec feature will always disable. [How] Separate fec debug flag and monitor patch Tested-by:
Lewis Huang <Lewis.Huang@amd.com> Reviewed-by:
Wenjing Liu <Wenjing.Liu@amd.com> Acked-by:
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