- 27 Jan, 2017 40 commits
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Huang Rui authored
Fixes: 9e8590861e9 ('drm/amdgpu: add parse clock gating state') Reported-by:Tom StDenis <Tom.StDenis@amd.com> Signed-off-by:
Huang Rui <ray.huang@amd.com> Reviewed-by:
Alex Deucher <alexander.deucher@amd.com> Signed-off-by:
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Xiangliang Yu authored
Current amdgpu reset process only works on bare-metal and for SRIOV many inside it need re-work to adapt to vf device. This is a temporary workaround to skip gpu reset. Signed-off-by:
Monk Liu <Monk.Liu@amd.com> Signed-off-by:
Xiangliang Yu <Xiangliang.Yu@amd.com> Reviewed-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
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Xiangliang Yu authored
Virtual display is default setting for virtualization, enable it. Signed-off-by:
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Xiangliang Yu authored
Call VI virtualization functions if device is Vf. Signed-off-by:
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Xiangliang Yu authored
For gpu vf device, first need to request full gpu access before accessing gpu registers, and release full gpu access after the access is done. Signed-off-by:
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Xiangliang Yu authored
VI has asic specific virt support, which including mailbox and golden registers init. Signed-off-by:
shaoyunl <Shaoyun.Liu@amd.com> Reviewed-by:
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Xiangliang Yu authored
Add high level interfaces that is not relate to specific asic. So asic files just need to implement the interfaces to support virtualization. Signed-off-by:
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Xiangliang Yu authored
For virtualization, it is must for driver to use KIQ to access registers when it is out of GPU full access mode. v2: agd: rebase Signed-off-by:
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Xiangliang Yu authored
Add new flag to define gpu runtime that is out of full gpu access. Signed-off-by:
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Xiangliang Yu authored
Implement emit_rreg/wreg function for kiq ring. Signed-off-by:
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Xiangliang Yu authored
During virtual runtime, need to send command to kiq ring to read/write GPU registers. Add two interface to support the two actions. Signed-off-by:
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Monk Liu authored
Make sure the CSA is mapped. v2: agd: rebase. Signed-off-by:
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Monk Liu authored
for SRIOV usage, CSA is only used per device and each VM will map on it. Signed-off-by:
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Monk Liu authored
and implement CSA functions in this file Signed-off-by:
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Nicolai Hähnle authored
Skip amdgpu_gem_va_update_vm otherwise. Also clean up the check for the non-shadow page tables using the new helper function. This fixes a crash with the stack trace: amdgpu_gem_va_update_vm -> amdgpu_vm_update_page_directory -> amdgpu_ttm_bind -> amdgpu_gtt_mgr_alloc v2: actually check bo->shadow instead of just checking bo twice Signed-off-by:
Nicolai Hähnle <nicolai.haehnle@amd.com> Reviewed-by:
Chunming Zhou <david1.zhou@amd.com> Reviewed-by:
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Nicolai Hähnle authored
Skip amdgpu_gem_va_update_vm when shadow the page directory is swapped out. Clean up the check for non-shadow BOs as well using the new helper function. This fixes a crash with the stack trace: amdgpu_gem_va_update_vm -> amdgpu_vm_update_page_directory -> amdgpu_ttm_bind -> amdgpu_gtt_mgr_alloc Signed-off-by:
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Nicolai Hähnle authored
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Nicolai Hähnle authored
This catches evictions of shadow page tables from the GART. Since shadow page tables are always stored in system memory, amdgpu_bo_move is never called for them. This fixes a crash during command submission that occurs when only a shadow page table and no other BOs were evicted since the last submission. Fixes: 1baa439f ("drm/amdgpu: allocate shadow for pd/pt bo V2") Signed-off-by:
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Nicolai Hähnle authored
Ensure that the driver can listen to evictions even when they don't take the path through ttm_bo_driver::move. This is crucial for amdgpu, which relies on an eviction counter to skip re-binding page tables when possible. Signed-off-by:
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Rex Zhu authored
1. disable vce cg when vce hw initialize. 2. initizlize vce clock to 10KHz fo dgpu, so no need to set bypass clock to vce. Change-Id: I934c2c4820cc95c1bfa2fa41ff0f40a0d3cd1c40 Signed-off-by:
Rex Zhu <Rex.Zhu@amd.com> Reviewed-by:
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Rex Zhu authored
in profiling mode, powerplay will fix power state as stable as possible.and disable gfx cg and LBPW feature. profile_standard: as a prerequisite, ensure power and thermal sustainable, set clocks ratio as close to the highest clock ratio as possible. profile_min_sclk: fix mclk as profile_normal, set lowest sclk profile_min_mclk: fix sclk as profile_normal, set lowest mclk profile_peak: set highest sclk and mclk, power and thermal not sustainable profile_exit: exit profile mode. enable gfx cg/lbpw feature. Signed-off-by:
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Rex Zhu authored
Updating SQ DIDT settings and block mask so SQ uses PCC on Polaris11. Signed-off-by:
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Rex Zhu authored
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Rex Zhu authored
following firmware's request. Signed-off-by:
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Rex Zhu authored
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Huang Rui authored
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Huang Rui authored
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Huang Rui authored
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Huang Rui authored
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Huang Rui authored
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Huang Rui authored
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Huang Rui authored
Suggested-by:
Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by:
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Huang Rui authored
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Xiangliang Yu authored
Call detection function driectly, so remove the interface. V2: ci and si also need to call the detect function. Reviewed-by:
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Xiangliang Yu authored
Move the detection forward into vi_set_ip_blocks function, then add ip blocks virtualization need if device is VF. V2: add ip blocks according to asic type. Reviewed-by:
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Xiangliang Yu authored
Use acronym to rename fields to make easy to spell out. Signed-off-by:
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Xiangliang Yu authored
KIQ is queue-memory based initialization method: setup KIQ queue firstly, then send command to KIQ to setup other queues, without accessing registers. For virtualization, need KIQ to access virtual function registers when running on guest mode. V2: use amdgpu_bo_create/free_kernel to allocate BO. Signed-off-by:
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Amber Lin authored
PCI I/O bar can be disabled in VBIOS to save the resource. It is often disabled in large aperture VBIOS. Don't call it an error. Signed-off-by:
Amber Lin <Amber.Lin@amd.com> Acked-by:
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Rex Zhu authored
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Rex Zhu authored
1. delete asic_smum_init functions, export asic private functions to smumgr directly, make code more readable. 2. create asic private data in asic_init_func. Signed-off-by:
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