- 12 Jun, 2019 14 commits
-
-
Tvrtko Ursulin authored
Only a few call sites remain which have been converted to uncore mmio accessors and so the macro can be removed. Signed-off-by:
Tvrtko Ursulin <tvrtko.ursulin@intel.com> Reviewed-by:
Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190611104548.30545-4-tvrtko.ursulin@linux.intel.com
-
Tvrtko Ursulin authored
Only a few call sites remain which have been converted to uncore mmio accessors and so the macro can be removed. ENGINE_POSTING_READ16 is added to replace one engine->mmio_base relative call site. Signed-off-by:
-
Tvrtko Ursulin authored
Only a few call sites remain which have been converted to uncore mmio accessors and so the macro can be removed. Signed-off-by:
-
Tvrtko Ursulin authored
Only a few call sites remain which have been converted to uncore mmio accessors and so the macro can be removed. Signed-off-by:
-
Chris Wilson authored
With async binding, we don't want to manage a bound/unbound list as we may end up running before we even acquire the pages. All that is required is keeping track of shrinkable objects, so reduce it to the minimum list. Fixes: 6951e589 ("drm/i915: Move GEM object domain management from struct_mutex to local") Signed-off-by:
Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by:
Matthew Auld <matthew.william.auld@gmail.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190612105720.30310-1-chris@chris-wilson.co.uk
-
Ville Syrjälä authored
All AML parts are either KBL ULX or CFL ULX so there is no point in keeping INTEL_SUBPLATFORM_AML around. As these are the only CFL ULX parts (normal CFL didn't have Y SKUs) so we'll just replace IS_AML_ULX with IS_CFL_ULX (it was already paired with IS_KBL_ULX which accounts for the other half of the AML parts). Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Cc: José Roberto de Souza <jose.souza@intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by:
Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190605162946.19223-2-ville.syrjala@linux.intel.comReviewed-by:
Rodrigo Vivi <rodrigo.vivi@intel.com>
-
Ville Syrjälä authored
Add a comma after the final entry to make diffs less obnoxious if we have to add further entries past the last one. Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Signed-off-by:
-
Ville Syrjälä authored
On non-ULT HSW the "special" WRPLL reference clock select actually means non-SSC. Take that into account when reading out the WRPLL state. Also the non-SSC reference may be either 24MHz or 135MHz, which we can read out from FUSE_STRAP3. The BDW docs actually say: "also indicates whether the CPU and PCH are in a single package or separate packages", so it may be that this is not actually required and we could just assume 135 MHz (just like the code already did). But it doesn't really hurt to read this out as the HSW docs aren't quite so clear. Signed-off-by:
Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
-
Ville Syrjälä authored
Only the non-SSC reference is truly supported for the LCPLL. Assert that it is indeed selected. Signed-off-by:
-
Ville Syrjälä authored
Get rid of the pointless LC_FREQ define. Signed-off-by:
-
Ville Syrjälä authored
Give the PLL control register bits better names on HSW/BDW. v2: Fix the copy paste fails in SPLL_REF defines (Maarten) Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Signed-off-by:
-
Ville Syrjälä authored
Our PCH refclk init code currently assumes that the PCH SSC reference can only be used for FDI. That is not true and it can be used by SPLL/WRPLL for eDP SSC or clock bending as well. Before we go reconfiguring it let's make sure no PLL is currently using the PCH SSC reference. For some reason the hw is not particularly upset about losing the clock if we immediately follow up with a modeset. Can't really explain why nothing times out during the crtc disable at least, but that's what the logs say. With fastboot the story is quite different and we lose the entire display if we turn off the PCH SSC reference when it's still being used. Since we totally skip configuring the PCH SSC reference it may not be in the proper state for FDI. Hopefully that won't be a problem in practice. We really should move this code to be part of the modeset seqeuence and properly deal with the potentially conflicting requirements imposed on PLL reference clocks. But that requires actual work. Let's toss in a TODO for that. v2: Pimp the commit message with the fastboot vs. not details Cc: Julius B. <freedesktop@blln.gr> Cc: Johannes Krampf <johannes.krampf@gmail.com> Tested-by:Johannes Krampf <johannes.krampf@gmail.com> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108773Signed-off-by:
-
Chris Wilson authored
We cannot allow ourselves to wait on the GPU while holding any lock as we may need to reset the GPU. While there is not an explicit lock between the two operations, lockdep cannot detect the dependency. So let's tell lockdep about the wait/reset dependency with an explicit lockmap. Signed-off-by:
Mika Kuoppala <mika.kuoppala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190612085246.16374-1-chris@chris-wilson.co.uk
-
Chris Wilson authored
If we don't give it a label, it does not appear as a configuration option. Signed-off-by:
-
- 11 Jun, 2019 7 commits
-
-
Lucas De Marchi authored
Like was done for ICL, let's convert the voltage level lookup to use frequency ranges rather than individual frequencies. For deciding the voltage, the individual value doesn't really matter. Signed-off-by:
Lucas De Marchi <lucas.demarchi@intel.com> Reviewed-by:
-
Lucas De Marchi authored
Like was done for ICL, let's convert the voltage level lookup to use frequency ranges rather than individual frequencies. For deciding the voltage, the individual value doesn't really matter. Signed-off-by:
-
Lucas De Marchi authored
Spec shows voltage level 0 as 307.2, 312, or lower and suggests to use range checks. Prepare for having other frequencies in these ranges by not comparing the exact frequency. v2: invert checks by comparing biggest cdclk first (suggested by Ville) Signed-off-by:
-
Tvrtko Ursulin authored
These functions operate on ggtt so make them take that directly as parameter. At the same time move the USES_GUC conditional down to intel_guc_reserve_ggtt_top for symmetry with intel_guc_reserved_gtt_size. v2: * Rename and move functions to be static in i915_gem_gtt.c (Michal) v3: * Add comment explaining reason for reservation, add assert and fix error message. (Michal) v4: * Fix checkpatch error. Signed-off-by:
Michal Wajdeczko <michal.wajdeczko@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190611122350.15060-1-tvrtko.ursulin@linux.intel.com
-
Tvrtko Ursulin authored
Reduces pointer chasing and gets more to the point. v2: * Tidy whitespace. * Tidy comment. (Michal) Signed-off-by:
-
Chris Wilson authored
Keeping the _hw_ in there does not help to distinguish it from its only brethren i915_ggtt, so drop it. Signed-off-by:
Matthew Auld <matthew.auld@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190611091238.15808-2-chris@chris-wilson.co.uk
-
Chris Wilson authored
Make the kref common to both derived structs (i915_ggtt and i915_ppgtt) so that we can safely reference count an abstract ctx->vm address space. Signed-off-by:
-
- 10 Jun, 2019 16 commits
-
-
Chris Wilson authored
The intent is to be able to update the mm.lists from inside an irqsoff section (e.g. from a softirq rcu workqueue), ergo we need to make the i915->mm.obj_lock irqsafe. v2: can_discard_pages() ensures we are shrinkable v3: Beware shadowing of 'flags' Fixes: 3b4fa964 ("drm/i915: Track the purgeable objects on a separate eviction list") Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110869Signed-off-by:
-
Chris Wilson authored
Before we commit ourselves to writing commands into the ringbuffer and submitting the request, allow signals to interrupt acquisition of the timeline mutex. We allow ourselves to be interrupted at any time later if we need to block for space in the ring, anyway. Signed-off-by:
-
Tvrtko Ursulin authored
The function operates on the render engine so make the input reflect it. v2: * Pass engine to read_subslice_reg. (Chris) * Drop inline from read_subslice_reg. Signed-off-by:
-
Tvrtko Ursulin authored
Now that all their users are gone we can remove the macros and accompanying duplicated comment. Signed-off-by:
-
Tvrtko Ursulin authored
More implicit dev_priv removal. Signed-off-by:
-
Tvrtko Ursulin authored
More implicit dev_priv removal. Signed-off-by:
-
Tvrtko Ursulin authored
More removal of implicit dev_priv. Signed-off-by:
-
Tvrtko Ursulin authored
No excuse for code located in intel_uncore.c to not use intel_uncore_ helpers. Signed-off-by:
-
Tvrtko Ursulin authored
On the path of removing mmio accessors with implicit dev_priv, easy first step is to remove all such unused macros. Signed-off-by:
-
Lionel Landwerlin authored
Gen10 added an additional NOA_WRITE register (high bits) and we forgot to whitelist it for userspace. Fixes: 95690a02 ("drm/i915/perf: enable perf support on CNL") Signed-off-by:
Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by:
Kenneth Graunke <kenneth@whitecape.org> Link: https://patchwork.freedesktop.org/patch/msgid/20190601225845.12600-1-lionel.g.landwerlin@intel.com
-
Tvrtko Ursulin authored
The code is logically about reset so it makes sense. It also enables making i915_clear_error_registers static. Signed-off-by:
-
Geert Uytterhoeven authored
Fix the grammar. Signed-off-by:
Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by:
-
Jani Nikula authored
This no longer exists. Reviewed-by:
-
Jani Nikula authored
Some function declarations in intel_drv.h were missed when intel_atomic_plane.h was created. Reviewed-by:
-
Jani Nikula authored
intel_mark_busy(), intel_mark_idle(), and skl_cdclk_get_vco() no longer exist. Reviewed-by:
-
Jani Nikula authored
Move more missed declarations from i915_drv.h to intel_pm.h. Reviewed-by:
-
- 09 Jun, 2019 2 commits
-
-
Daniele Ceraolo Spurio authored
The size has been increased to 2MB starting from Gen11. GuC and HuC FWs fit in 1MB so we were fine even with the legacy define, but let's still move to the correct one before the blobs grow to avoid being caught off guard in the future. v2: return early if the platform doesn't have GuC, fix nits (Michal) Bspec: 12690 Signed-off-by:
Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Cc: Michal Wajdeczko <michal.wajdeczko@intel.com> Reviewed-by:
Stuart Summers <stuart.summers@intel.com> [ickle: use SZ consistently] Signed-off-by:
-
Daniele Ceraolo Spurio authored
Now that we've moved the Gen9 GuC blobs to version 32 we have CTB support on all gens, so no need to restrict the usage to Gen11+. Note that MMIO communication is still required for CTB initialization. v2: fix commit message nits (Michal) Signed-off-by:
-
- 08 Jun, 2019 1 commit
-
-
Hans de Goede authored
The GOP sometimes initializes the pclk at a (slightly) different frequency then the pclk which we've calculated. This commit makes the DSI code read-back the pclk set by the GOP and if that is within a reasonable margin of the calculated pclk, uses that instead. This fixes the first modeset being a full modeset instead of a fast modeset on systems where the GOP pclk is different. Changes in v2: -Use intel_encoder_current_mode() to get the pclk setup by the GOP Changes in v3: -Back to the readback approach, skipping the dsi_pll.ctrl / .dev checks in intel_pipe_config_compare() when adjust is set leads to: [drm:pipe_config_err [i915]] *ERROR* mismatch in dsi_pll.ctrl (...) [drm:pipe_config_err [i915]] *ERROR* mismatch in dsi_pll.div (...) -Do the readback and pclk overriding from vlv_dsi_init(), rather then from intel_dsi_vbt_init() as the vbt code should not be touching the hw Reviewed-by:
Hans de Goede <hdegoede@redhat.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190605181735.7020-3-hdegoede@redhat.com
-
