- 02 Jan, 2023 5 commits
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Krzysztof Kozlowski authored
Bindings expect power domains to follow generic naming pattern: sm8250-hdk.dtb: psci: 'cpu-cluster0', 'cpu0', 'cpu1', 'cpu2', 'cpu3', 'cpu4', 'cpu5', 'cpu6', 'cpu7' do not match any of the regexes: '^power-domain-', 'pinctrl-[0-9]+' Signed-off-by:Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by:
Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by:
Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230102085452.10753-4-krzysztof.kozlowski@linaro.org
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Krzysztof Kozlowski authored
Bindings expect power domains to follow generic naming pattern: sm8150-hdk.dtb: psci: 'cpu-cluster0', 'cpu0', 'cpu1', 'cpu2', 'cpu3', 'cpu4', 'cpu5', 'cpu6', 'cpu7' do not match any of the regexes: '^power-domain-', 'pinctrl-[0-9]+' Signed-off-by: -
Krzysztof Kozlowski authored
Bindings expect power domains to follow generic naming pattern: sm6375-sony-xperia-murray-pdx225.dtb: psci: 'cpu-cluster0', 'cpu0', 'cpu1', 'cpu2', 'cpu3', 'cpu4', 'cpu5', 'cpu6', 'cpu7' do not match any of the regexes: '^power-domain-', 'pinctrl-[0-9]+' Signed-off-by: -
Krzysztof Kozlowski authored
Bindings expect power domains to follow generic naming pattern: sc8280xp-crd.dtb: psci: 'cpu-cluster0', 'cpu0', 'cpu1', 'cpu2', 'cpu3', 'cpu4', 'cpu5', 'cpu6', 'cpu7' do not match any of the regexes: '^power-domain-', 'pinctrl-[0-9]+' Signed-off-by: -
Krzysztof Kozlowski authored
Soundwire is a bus and VA-macro requires a supply, thus both are expected to be explicitly enabled and populated by board DTS. The HDK8450 already enables Soundwire devices, except swr4 which as a result of this commit will stay disabled. Signed-off-by:
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- 29 Dec, 2022 35 commits
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Krzysztof Kozlowski authored
Node names should be generic so use consistently speaker-amp for CS35L41 speaker amplifier. Signed-off-by:
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Krzysztof Kozlowski authored
Bindings expect GCC clocks in other order: sm8450-hdk.dtb: clock-controller@100000: clock-names:1: 'sleep_clk' was expected Signed-off-by:
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Krzysztof Kozlowski authored
Neither qcom,sm8250-lpass-va-macro bindings nor the driver use "clock-frequency" property. Signed-off-by:
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Krzysztof Kozlowski authored
The node names should be generic and the bindings expect "bus" for simple-bus nodes: msm8996-mtp.dtb: agnoc@0: $nodename:0: 'agnoc@0' does not match '^bus(@[0-9a-f]+)?$' Signed-off-by:
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Marijn Suijten authored
Enable I2C Serial Engines 1, 2 and 3 which are known to have hardware connected to them, leaving the rest disabled to save on power. For this, only GPI DMA 0 and QUP 0 need to be enabled, as nothing seems to be connected to Serial Engines on GPU DMA 1 / QUP 1. Beyond this downstream only defines a UART console available on Serial Engine 4 which also resides on QUP 0. Signed-off-by:
Marijn Suijten <marijn.suijten@somainline.org> Reviewed-by:
Martin Botka <martin.botka@somainline.org> Reviewed-by:
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Marijn Suijten authored
Add Qualcomm Universal Peripheral nodes with SPI and I2C Serial Engines. QUP 0 only has two SPIs at index 0 and 2, QUP 1 has four SPIs with a gap in the middle (ranging from 5-9 with SPI 7 missing). Both QUPs have 5 I2C Serial Engines. [Marijn: Add iommus, reword patch description, reorder all properties, sort based on address, use QCOM_GPI_ constants, drop dma cells from 5 to 3] Signed-off-by:
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Martin Botka authored
Add pin setup for SPI/I2C Serial Engines that are supported under the Qualcomm Universal Peripheral found on SM6125. [Un-nest pins, remove duplicate pins= properties, follow new node naming conventions, fix qup_14 -> qup14 function typo] Signed-off-by:
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Marijn Suijten authored
- Remove autorepeat (leave key repetition to userspace); - Remove unneeded status = "okay" (this is the default); - Remove unneeded linux,input-type <EV_KEY> (this is the default for gpio-keys); - Allow the interrupt line for this button to be disabled; - Use a full, descriptive node name; - Set proper bias on the GPIO via pinctrl; - Sort properties; - Replace deprecated gpio-key,wakeup property with wakeup-source. Fixes: 82e17838 ("arm64: dts: qcom: sm6125: Add support for Sony Xperia 10II") Signed-off-by:
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Martin Botka authored
Add nodes for GPI DMA hosts on SM6125. [Marijn: reorder properties, use sdm845 fallback compatible, disable by default, use 3 instead of 5 dma cells] Signed-off-by:
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AngeloGioacchino Del Regno authored
Add an IOMMU context to the USB DWC3 controller, required to get USB functionality upon enablement of apps_smmu. Signed-off-by:
AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> Signed-off-by:
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Marijn Suijten authored
When enabling the APPS SMMU the mainline driver reconfigures the SMMU from its bootloader configuration, losing the stream mapping for (among which) the SDHCI hardware and breaking its ADMA feature. This feature can be disabled with: sdhci.debug_quirks=0x40 But it is of course desired to have this feature enabled and working through the SMMU. Signed-off-by: -
Martin Botka authored
Add a node for the APPS SMMU, to which various devices such as USB and storage nodes are connected. [Marijn: add the new, generic, "qcom,smmu-500" compatible, add patch description, reorder # properties] Signed-off-by:
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Marijn Suijten authored
Reorder the clocks and corresponding names to match the QUSB2 phy schema, fixing the following CHECK_DTBS errors: arch/arm64/boot/dts/qcom/sm6125-sony-xperia-seine-pdx201.dtb: phy@1613000: clock-names:0: 'cfg_ahb' was expected From schema: /newdata/aosp-r/kernel/mainline/kernel/Documentation/devicetree/bindings/phy/qcom,qusb2-phy.yaml arch/arm64/boot/dts/qcom/sm6125-sony-xperia-seine-pdx201.dtb: phy@1613000: clock-names:1: 'ref' was expected From schema: /newdata/aosp-r/kernel/mainline/kernel/Documentation/devicetree/bindings/phy/qcom,qusb2-phy.yaml Fixes: cff4bbaf ("arm64: dts: qcom: Add support for SM6125") Signed-off-by: -
Marijn Suijten authored
Ensure the eMMC and SD Card always have a predictable slot index by predetermining them via aliases. Signed-off-by:
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Marijn Suijten authored
Sony's seine board features an SD Card slot on SDHCI 2, that is to be powered by l5 and l22. The card detect pin is already biased via updates on the generic sdc2_*_state pinctrl nodes. As usual regulator voltages are decreased to the maximum voted by the downstream driver for safety. SDHCI 2 is the only hardware block feeding off of these. Signed-off-by:
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Marijn Suijten authored
While SDHCI 1 appears to work out of the box, we cannot rely on the bootloader-enabled regulators nor expect them to remain enabled (e.g. when finally dropping pd_ignore_unused). Provide it the necessary l24 and l11 regulators now that PM6125 regulators have been made available on this board. As usual regulator voltages are decreased to the maximum voted by the downstream driver for safety. No other hardware feeds off of these regulators anyway (except UFS, which isn't used on the seine board in favour of a DV6DMB eMMC card connected to SDHCI 1). Signed-off-by:
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Marijn Suijten authored
Document the use of l7, l10 and l15 in the High Speed Qualcomm USB2 PHY, in order to keep the regulators voted on when USB is active. Signed-off-by:
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Marijn Suijten authored
Configure PM6125 regulators based on availability and voltages defined downstream, to allow powering up (and/or keeping powered) other hardware blocks going forward. Signed-off-by:
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Marijn Suijten authored
Pinctrl states typically collate multiple related pins. In the case of gpio-keys there's no hardware-defined relation at all except all pins representing a key; and especially on Sony's lena board there's only one pin regardless. Flatten it similar to other boards [1]. As a drive-by fix, clean up the label string. [1]: https://lore.kernel.org/linux-arm-msm/11174eb6-0a9d-7df1-6f06-da4010f76453@linaro.org/ Fixes: 2b8bbe98 ("arm64: dts: qcom: sm6350-lena: Include pm6350 and configure buttons") Signed-off-by:
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Bryan O'Donoghue authored
Add silicon specific compatible qcom,sm8250-dsi-ctrl to the mdss-dsi-ctrl block. This allows us to differentiate the specific bindings for sm8250 against the yaml documentation. Reviewed-by:
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by:
Bryan O'Donoghue <bryan.odonoghue@linaro.org> Signed-off-by:
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Bryan O'Donoghue authored
Add silicon specific compatible qcom,sdm845-dsi-ctrl to the mdss-dsi-ctrl block. This allows us to differentiate the specific bindings for sdm845 against the yaml documentation. Reviewed-by:
Douglas Anderson <dianders@chromium.org> Reviewed-by:
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Bryan O'Donoghue authored
Add silicon specific compatible qcom,sdm660-dsi-ctrl to the mdss-dsi-ctrl block. This allows us to differentiate the specific bindings for sdm660 against the yaml documentation. Signed-off-by:
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Bryan O'Donoghue authored
The sdm630 can use the sdm660 mdss-dsi-ctrl compat. Currently it has the same set of binding dependencies as sdm660. Suggested-by:
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Bryan O'Donoghue authored
Add silicon specific compatible qcom,sc7280-dsi-ctrl to the mdss-dsi-ctrl block. This allows us to differentiate the specific bindings for sc7280 against the yaml documentation. Reviewed-by:
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Bryan O'Donoghue authored
Add silicon specific compatible qcom,sc7180-dsi-ctrl to the mdss-dsi-ctrl block. This allows us to differentiate the specific bindings for sc7180 against the yaml documentation. Reviewed-by:
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Bryan O'Donoghue authored
Add silicon specific compatible qcom,msm8996-dsi-ctrl to the mdss-dsi-ctrl block. This allows us to differentiate the specific bindings for msm8996 against the yaml documentation. Reviewed-by:
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Bryan O'Donoghue authored
Add silicon specific compatible qcom,msm8953-dsi-ctrl to the mdss-dsi-ctrl block. This allows us to differentiate the specific bindings for msm8953 against the yaml documentation. Signed-off-by:
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Bryan O'Donoghue authored
Add silicon specific compatible qcom,msm8916-dsi-ctrl to the mdss-dsi-ctrl block. This allows us to differentiate the specific bindings for msm8916 against the yaml documentation. Reviewed-by:
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Krzysztof Kozlowski authored
The bindings expect "mmc" for MMC/SDHCI nodes: sm8350-sony-xperia-sagami-pdx214.dtb: sdhci@8804000: $nodename:0: 'sdhci@8804000' does not match '^mmc(@.*)?$' Signed-off-by:
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Alex Elder authored
IPA is only needed on a platform if it includes a modem, and not all SC7280 SoC variants do. The file "sc7280-herobrine-lte-sku.dtsi" is used to encapsulate definitions related to Chrome OS SC7280 devices where a modem is present, and that's the proper place for the IPA node to be enabled. Currently IPA is enabled in "sc7280-idp.dtsi", which is included by DTS files for Qualcomm reference platforms (all of which include the modem). That also includes "sc7280-herobrine-lte-sku.dtsi", so enabling IPA there would make it unnecessary for "sc7280-idp.dtsi" to enable it. The only other place IPA is enabled is "sc7280-qcard.dtsi". That file is included only by "sc7280-herobrine.dtsi", which is (eventually) included only by these top-level DTS files: sc7280-herobrine-crd.dts sc7280-herobrine-herobrine-r1.dts sc7280-herobrine-evoker.dts sc7280-herobrine-evoker-lte.dts sc7280-herobrine-villager-r0.dts sc7280-herobrine-villager-r1.dts sc7280-herobrine-villager-r1-lte.dts All of but two of these include "sc7280-herobrine-lte-sku.dtsi", and for those cases, enabling IPA there means there is no need for it to be enabled in "sc7280-qcard.dtsi". The two remaining cases will no longer enable IPA as a result of this change: sc7280-herobrine-evoker.dts sc7280-herobrine-villager-r1.dts Both of these have "lte" counterparts, and are meant to represent board variants that do *not* have a modem. This is exactly the desired configuration. Signed-off-by:
Alex Elder <elder@linaro.org> Reviewed-by:
Sibi Sankar <quic_sibis@quicinc.com> Tested-by:
Matthias Kaehlcke <mka@chromium.org> Reviewed-by:
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Krzysztof Kozlowski authored
This board uses RPMH, specifies "regulator-allow-set-load" for LDOs, but doesn't specify any modes with "regulator-allowed-modes": sm8350-sony-xperia-sagami-pdx214.dtb: regulators-0: ldo5: 'regulator-allowed-modes' is a dependency of 'regulator-allow-set-load' Signed-off-by:
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Konrad Dybcio authored
Add required nodes for MDSS and hook up provided clocks in DISPCC. This setup is almost identical to 8[23]50. Tested-by: Marijn Suijten <marijn.suijten@somainline.org> # Xperia 5 Reviewed-by:
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Konrad Dybcio authored
Years after the SoC support has been added, it's high time for it to get dispcc going. Add the node to ensure that. Tested-by: Marijn Suijten <marijn.suijten@somainline.org> # Xperia 5 Reviewed-by:
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Krzysztof Kozlowski authored
Add full cache description to DTS to avoid: 1. "Early cacheinfo failed" warnings, 2. Cache topology detection which leads to early memory allocations and "BUG: sleeping function called from invalid context" on PREEMPT_RT kernel: smp: Bringing up secondary CPUs ... Detected VIPT I-cache on CPU1 BUG: sleeping function called from invalid context at kernel/locking/spinlock_rt.c:46 in_atomic(): 1, irqs_disabled(): 128, non_block: 0, pid: 0, name: swapper/1 preempt_count: 1, expected: 0 RCU nest depth: 1, expected: 1 3 locks held by swapper/1/0: #0: ffff5e337eee5f18 (&pcp->lock){+.+.}-{3:3}, at: get_page_from_freelist+0x20c/0xffc #1: ffffa9e24a900b18 (rcu_read_lock){....}-{1:3}, at: rt_spin_trylock+0x40/0xe4 #2: ffff5e337efc8918 (&zone->lock){+.+.}-{3:3}, at: rmqueue_bulk+0x54/0x720 irq event stamp: 0 Call trace: __might_resched+0x17c/0x214 rt_spin_lock+0x5c/0x100 rmqueue_bulk+0x54/0x720 get_page_from_freelist+0xcfc/0xffc __alloc_pages+0xec/0x1150 alloc_page_interleave+0x1c/0xd0 alloc_pages+0xec/0x160 new_slab+0x330/0x454 ___slab_alloc+0x5b8/0xba0 __kmem_cache_alloc_node+0xf4/0x20c __kmalloc+0x60/0x100 detect_cache_attributes+0x2a8/0x5a0 update_siblings_masks+0x28/0x300 store_cpu_topology+0x58/0x70 secondary_start_kernel+0xc8/0x154 Signed-off-by: -
Pierre Gondois authored
The DeviceTree Specification v0.3 specifies that the cache node 'compatible' and 'cache-level' properties are 'required'. Cf. s3.8 Multi-level and Shared Cache Nodes The 'cache-unified' property should be present if one of the properties for unified cache is present ('cache-size', ...). Update the Device Trees accordingly. About msm8953.dtsi: According to the Devicetree Specification v0.3, s3.7.3 'Internal (L1) Cache Properties', cache-unified: If present, specifies the cache has a unified or- ganization. If not present, specifies that the cache has a Harvard architecture with separate caches for instructions and data. Plus, the 'cache-level' property seems to be reserved to higher cache levels (cf s3.8). To describe a l1 data/instruction cache couple, no cache information should be described. Remove the l1 cache nodes. Signed-off-by:Pierre Gondois <pierre.gondois@arm.com> [bjorn: Moved "qcom" to $subject prefix] Signed-off-by:
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