- 03 Apr, 2017 6 commits
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Geert Uytterhoeven authored
Add the Z2 clock (Cortex-A7 CPU core clock), which uses a fixed divider, and link the first CPU node to it. Signed-off-by:
Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by:
Simon Horman <horms+renesas@verge.net.au>
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Geert Uytterhoeven authored
Unlike other R-Car Gen2 SoCs with Cortex-A15 CPU cores, R-Car V2H does not have a programmable Z clock (Cortex-A15 CPU core clock), but uses a fixed divider. This is similar to the Z2 clock (Cortex-A7 CPU core clock) on R-Car E2. Hence: - Remove the Z clock output from the cpg_clocks node, as this implied a programmable clock, - Add the Z clock as a fixed factor clock, - Let the first CPU node point to the new Z clock, - Remove the Z clock index from the bindings (this definition was used by r8a7792.dtsi only, and was not a contract between DT and driver). Fixes: 7c4163aa ("ARM: dts: r8a7792: initial SoC device tree") Signed-off-by: -
Geert Uytterhoeven authored
The SSI-ALL gate clock is located in between the P clock and the individual SSI[0-9] clocks, hence the former should be listed as their parent. Fixes: 072d3265 ("ARM: dts: r8a7793: add MSTP10 clocks to device tree") Signed-off-by:
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Geert Uytterhoeven authored
The SSI-ALL gate clock is located in between the P clock and the individual SSI[0-9] clocks, hence the former should be listed as their parent. Fixes: ee914152 ("ARM: shmobile: r8a7791: add MSTP10 support on DTSI") Signed-off-by:
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Geert Uytterhoeven authored
The SSI-ALL gate clock is located in between the P clock and the individual SSI[0-9] clocks, hence the former should be listed as their parent. Fixes: bcde3722 ("ARM: shmobile: r8a7790: add MSTP10 support on DTSI") Signed-off-by:
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Chris Brandt authored
Technically, the Ethernet block is run off the 133MHz Bus (B) clock, not the 33MHz Peripheral 0 (P0) clock. Fixes: 969244f9 ("ARM: dts: r7s72100: add ethernet clock to device tree") Signed-off-by:
Chris Brandt <chris.brandt@renesas.com> Reviewed-by:
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- 28 Mar, 2017 4 commits
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Geert Uytterhoeven authored
The second channel of the display unit uses a different module clock than the first channel. Fixes: 84e734f4 ("ARM: dts: silk: add DU DT support") Signed-off-by:
Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by:
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Geert Uytterhoeven authored
The second channel of the display unit uses a different module clock than the first channel. Fixes: 876e7fb9 ("ARM: shmobile: r8a7794: alt: Enable VGA port") Signed-off-by:
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Geert Uytterhoeven authored
The second channel of the display unit uses a different module clock than the first channel. Fixes: 46c4f13d ("ARM: shmobile: r8a7794: Add DU node to device tree") Signed-off-by:
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Geert Uytterhoeven authored
Add the missing module clock for the second channel of the display unit. Signed-off-by:
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- 24 Mar, 2017 1 commit
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Chris Brandt authored
Reported-by:
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- 21 Mar, 2017 2 commits
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Geert Uytterhoeven authored
Add properties to describe the reset topology for on-SoC devices: - Add the "#reset-cells" property to the CPG/MSSR device node, - Add resets and reset-names properties to the various device nodes. This allows to reset SoC devices using the Reset Controller API. Note that all resets added match the corresponding module clocks. Signed-off-by:
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Geert Uytterhoeven authored
Add properties to describe the reset topology for on-SoC devices: - Add the "#reset-cells" property to the CPG/MSSR device node, - Add resets and reset-names properties to the various device nodes. This allows to reset SoC devices using the Reset Controller API. Note that all resets added match the corresponding module clocks. Signed-off-by:
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- 13 Mar, 2017 10 commits
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Geert Uytterhoeven authored
The scif_clk device node is already enabled in r8a7794.dtsi, so there is no need to update its status again. Signed-off-by:
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Geert Uytterhoeven authored
The scif_clk device node is already enabled in r8a7794.dtsi, so there is no need to update its status again. Signed-off-by:
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Geert Uytterhoeven authored
The scif_clk device node is already enabled in r8a7793.dtsi, so there is no need to update its status again. Signed-off-by:
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Geert Uytterhoeven authored
The pcie_bus_clk device node is already enabled in r8a7791.dtsi, so there is no need to update its status again. Signed-off-by:
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Geert Uytterhoeven authored
The scif_clk and pcie_bus_clk device nodes are already enabled in r8a7791.dtsi, so there is no need to update their statuses again. Signed-off-by:
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Geert Uytterhoeven authored
The scif_clk device node is already enabled in r8a7790.dtsi, so there is no need to update its status again. Signed-off-by:
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Geert Uytterhoeven authored
The scif_clk device node is already enabled in r8a7779.dtsi, so there is no need to update its status again. Signed-off-by:
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Geert Uytterhoeven authored
The scif_clk device node is already enabled in r8a7778.dtsi, so there is no need to update its status again. Signed-off-by:
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Geert Uytterhoeven authored
While status "ok" does work, the canonical form is "okay", so update the few places that used the former. Signed-off-by:
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Geert Uytterhoeven authored
Link the ARM GIC to the INTC-SYS module clock, and add it to the "always on" PM Domain, so it can be power managed using that clock. Note that currently the GIC-400 driver doesn't support module clocks nor Runtime PM, so this must be handled as a critical clock. Signed-off-by:
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- 10 Mar, 2017 8 commits
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Kuninori Morimoto authored
Current Audio-DMAC is assigned "rx" as Audio-DMAC0, "tx" as Audio-DMAC1. Thus, DVC "tx" should be assigned as Audio-DMAC1, instead of Audio-DMAC0. Because of this, current platform board (using SRC/DVC/SSI) Playback/Capture both will use same Audio-DMAC0 (but it depends on audio data path). First note is that this "rx" and "tx" are from each IP point, it doesn't mean Playback/Capture. Second note is that Audio DMAC assigned on DT is only for Audio-DMAC, Audio-DMAC-peri-peri has no entry. => Audio-DMAC -> Audio-DMAC-peri-peri -- HW connection Playback case [Mem] => [SRC]--[DVC] -> [SSI]--[Codec] rx ~~~~~~~~~~~~ Capture [Mem] <= [DVC]--[SRC] <- [SSI]--[Codec] tx ~~~~~~~~~~~~ Signed-off-by:
Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by:
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Kuninori Morimoto authored
Current Audio-DMAC is assigned "rx" as Audio-DMAC0, "tx" as Audio-DMAC1. Thus, DVC "tx" should be assigned as Audio-DMAC1, instead of Audio-DMAC0. Because of this, current platform board (using SRC/DVC/SSI) Playback/Capture both will use same Audio-DMAC0 (but it depends on audio data path). First note is that this "rx" and "tx" are from each IP point, it doesn't mean Playback/Capture. Second note is that Audio DMAC assigned on DT is only for Audio-DMAC, Audio-DMAC-peri-peri has no entry. => Audio-DMAC -> Audio-DMAC-peri-peri -- HW connection Playback case [Mem] => [SRC]--[DVC] -> [SSI]--[Codec] rx ~~~~~~~~~~~~ Capture [Mem] <= [DVC]--[SRC] <- [SSI]--[Codec] tx ~~~~~~~~~~~~ Signed-off-by:
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Geert Uytterhoeven authored
Link the ARM GIC to the INTC-SYS module clock, and add it to the "always on" PM Domain, so it can be power managed using that clock. Note that currently the GIC-400 driver doesn't support module clocks nor Runtime PM, so this must be handled as a critical clock. Signed-off-by:
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Geert Uytterhoeven authored
Link the ARM GIC to the INTC-SYS module clock, and add it to the "always on" PM Domain, so it can be power managed using that clock. Note that currently the GIC-400 driver doesn't support module clocks nor Runtime PM, so this must be handled as a critical clock. Signed-off-by:
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Geert Uytterhoeven authored
Link the ARM GIC to the INTC-SYS module clock, and add it to the "always on" PM Domain, so it can be power managed using that clock. Note that currently the GIC-400 driver doesn't support module clocks nor Runtime PM, so this must be handled as a critical clock. Signed-off-by:
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Geert Uytterhoeven authored
Link the ARM GIC to the INTC-SYS module clock, and add it to the "always on" PM Domain, so it can be power managed using that clock. Note that currently the GIC-400 driver doesn't support module clocks nor Runtime PM, so this must be handled as a critical clock. Signed-off-by:
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Geert Uytterhoeven authored
Link the ARM GIC to the INTC-SYS module clock and the C4 power domain, so it can be power managed using that clock in the future. Note that currently the GIC-400 driver doesn't support module clocks nor Runtime PM, so this must be handled as a critical clock. Signed-off-by:
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Chris Brandt authored
Add watchdog timer support for RZ/A1. For the RZ/A1, the only way to do a reset is to overflow the WDT, so this is useful even if you don't need the watchdog functionality. Signed-off-by:
Guenter Roeck <linux@roeck-us.net> Signed-off-by:
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- 07 Mar, 2017 9 commits
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Kuninori Morimoto authored
Current Audio-DMAC is assigned "rx" as Audio-DMAC0, "tx" as Audio-DMAC1. Thus, DVC "tx" should be assigned as Audio-DMAC1, instead of Audio-DMAC0. Because of this, current platform board (using SRC/DVC/SSI) Playback/Capture both will use same Audio-DMAC0 (but it depends on data path). First note is that this "rx" and "tx" are from each IP point, it doesn't mean Playback/Capture. Second note is that Audio DMAC assigned on DT is only for Audio-DMAC, Audio-DMAC-peri-peri has no entry. => Audio-DMAC -> Audio-DMAC-peri-peri -- HW connection Playback case [Mem] => [SRC]--[DVC] -> [SSI]--[Codec] rx ~~~~~~~~~~~~ Capture [Mem] <= [DVC]--[SRC] <- [SSI]--[Codec] tx ~~~~~~~~~~~~ Signed-off-by:
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Geert Uytterhoeven authored
The Cortex-A7 cache controller is an integrated controller, and thus the device node representing it should not have a unit-addresses or reg property. Fixes: 34ea4b4a ("ARM: dts: r8a7794: Fix W=1 dtc warnings") Signed-off-by:
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Geert Uytterhoeven authored
The Cortex-A15 cache controller is an integrated controller, and thus the device node representing it should not have a unit-addresses or reg property. Fixes: ad53f5f0 ("ARM: dts: r8a7793: Fix W=1 dtc warnings") Signed-off-by:
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Geert Uytterhoeven authored
The Cortex-A15 cache controller is an integrated controller, and thus the device node representing it should not have a unit-addresses or reg property. Fixes: 7c4163aa ("ARM: dts: r8a7792: initial SoC device tree") Signed-off-by:
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Geert Uytterhoeven authored
The Cortex-A15 cache controller is an integrated controller, and thus the device node representing it should not have a unit-addresses or reg property. Fixes: 6f9314ce ("ARM: dts: r8a7791: Fix W=1 dtc warnings") Signed-off-by:
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Geert Uytterhoeven authored
The Cortex-A15/A7 cache controllers are integrated controllers, and thus the device nodes representing them should not have unit-addresses or reg properties. Fixes: 2c3de367 ("ARM: dts: r8a7790: Fix W=1 dtc warnings") Signed-off-by:
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Geert Uytterhoeven authored
The Cortex-A7 cache controller is an integrated controller, and thus the device node representing it should not have a unit-addresses or reg property. Fixes: c9536024 ("ARM: dts: r8a7745: initial SoC device tree") Signed-off-by:
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Geert Uytterhoeven authored
The Cortex-A15 cache controller is an integrated controller, and thus the device node representing it should not have a unit-addresses or reg property. Fixes: 34e8d993 ("ARM: dts: r8a7743: initial SoC device tree") Signed-off-by:
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Geert Uytterhoeven authored
The Cortex-A15/A7 cache controllers are integrated controllers, and thus the device nodes representing them should not have unit-addresses or reg properties. Fixes: b0da45c6 ("ARM: dts: r8a73a4: Fix W=1 dtc warnings") Signed-off-by:
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