- 27 Oct, 2022 37 commits
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Ao Zhong authored
pipes[pipe_cnt].pipe.src.dcc_fraction_of_zs_req_luma = 0; pipes[pipe_cnt].pipe.src.dcc_fraction_of_zs_req_chroma = 0; these two operations in dcn32/dcn32_resource.c still need to use FPU, This will cause compilation to fail on ARM64 platforms because -mgeneral-regs-only is enabled by default to disable the hardware FPU. Therefore, imitate the dcn31_zero_pipe_dcc_fraction function in dml/dcn31/dcn31_fpu.c, declare the dcn32_zero_pipe_dcc_fraction function in dcn32_fpu.c, and move above two operations into this function. Reviewed-by:
Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by:
Ao Zhong <hacc1225@gmail.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Ao Zhong authored
In the process of enabling DCN support for arm64, I found that the dcn10_resource_construct_fp function in dcn10/dcn10_resource.c still needs to use FPU. This will cause compilation to fail on ARM64 platforms because -mgeneral-regs-only is enabled by default to disable the hardware FPU. So move dcn10_resource_construct_fp from dcn10 folder to dml/dcn10 folder to enable hardware FPU for that function. Reviewed-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
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Graham Sider authored
MES scheduler and kiq versions are stored in mes.sched_version and mes.kiq_version, respectively, which are read from a register after their queues are initialized. Remove mes.ucode_fw_version and mes.data_fw_version which tried to read this versioning info from the firmware headers (which don't contain this information). Signed-off-by:
Graham Sider <Graham.Sider@amd.com> Reviewed-by:
Jack Xiao <Jack.Xiao@amd.com> Signed-off-by:
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Graham Sider authored
Use mes.sched_version, mes.kiq_version for debugfs as mes.ucode_fw_version does not contain correct versioning information. Signed-off-by:
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Alan Liu authored
[Why] Before we call psp_securedisplay_invoke(), we call psp_prep_securedisplay_cmd_buf() to prepare and initialize the command buffer. However, we didn't use the mutex_lock to protect the status of command buffer. So when multiple threads are using the command buffer, after thread A return from psp_securedisplay_invoke() and the command buffer status is set to SUCCESS, another thread B may call psp_prep_securedisplay_cmd_buf() and initialize the status to FAILURE again, and cause Thread A to get a failure return status. [How] Move the mutex_lock out of psp_securedisplay_invoke() to its caller to cover psp_prep_securedisplay_cmd_buf() and the code checking the return status of command buffer. Signed-off-by:
Alan Liu <HaoPing.Liu@amd.com> Reviewed-by:
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Tao Zhou authored
Make the code simpler. Signed-off-by:
Tao Zhou <tao.zhou1@amd.com> Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
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Tao Zhou authored
For MCA poison, if unmap queue fails, only gpu reset should be triggered without page retirement handling, MCA notifier will do it. v2: handle MCA poison consumption in umc_poison_handler directly. Signed-off-by:
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Tao Zhou authored
Make the code more readable. Signed-off-by:
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Tao Zhou authored
Define page retirement functions for MCA platform. v2: remove page retirement handling from MCA poison handler, let MCA notifier do page retirement. v3: remove specific poison handler for MCA to simplify code. Signed-off-by: -
Paulo Miguel Almeida authored
struct cdit_header was never used across any of the amd drivers nor this is exposed to UAPI so it can be removed. This patch removes struct cdit_header and refactor code accordingly Signed-off-by:
Paulo Miguel Almeida <paulo.miguel.almeida.rodenas@gmail.com> Reviewed-by:
Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by:
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Paulo Miguel Almeida authored
kfd_pm4_headers_diq.h header is a leftover from the old H/W debugger module support added on commit fbeb661b ("drm/amdkfd: Add skeleton H/W debugger module support"). That implementation was removed after a while and the last file that included that header was removed on commit 5bdd3eb2 ("drm/amdkfd: Remove unused old debugger implementation"). This patch removes the unused header file kfd_pm4_headers_diq.h Signed-off-by:
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Fangzhi Zuo authored
[Why] Invalidate unsupported 420 modes on HDMI TMDS. HDMI TMDS does not support ODM. Any modes that are horizontally wider than 4096, cannot be supported via TMDS. So they must be filtered out and should not pass validation. [How] Create fake plane for the new stream, and validate global state by going through dml validation routine. Tested-by:
Mark Broadworth <mark.broadworth@amd.com> Acked-by:
Fangzhi Zuo <Jerry.Zuo@amd.com> Signed-off-by:
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Rodrigo Siqueira authored
The file dc.c has multiple comments that do not follow the kernel-doc or are made in a distracting way. This commit alleviates part of this issue by reorganizing some comments inside the dc file. Signed-off-by:
Hamza Mahfooz <hamza.mahfooz@amd.com> Signed-off-by:
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Aric Cyr authored
DC version 3.2.209 brings along the following: * Improve color manipulation * Add corrections to DML and some flag configuration * Updates for DCN32x * Expand kernel-doc Tested-by:
Aric Cyr <Aric.Cyr@amd.com> Signed-off-by:
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Yifan Zhang authored
This patch to fix the gdm3 start failure with virual display: /usr/libexec/gdm-x-session[1711]: (II) AMDGPU(0): Setting screen physical size to 270 x 203 /usr/libexec/gdm-x-session[1711]: (EE) AMDGPU(0): Failed to make import prime FD as pixmap: 22 /usr/libexec/gdm-x-session[1711]: (EE) AMDGPU(0): failed to set mode: Invalid argument /usr/libexec/gdm-x-session[1711]: (WW) AMDGPU(0): Failed to set mode on CRTC 0 /usr/libexec/gdm-x-session[1711]: (EE) AMDGPU(0): Failed to enable any CRTC gnome-shell[1840]: Running GNOME Shell (using mutter 42.2) as a X11 window and compositing manager /usr/libexec/gdm-x-session[1711]: (EE) AMDGPU(0): failed to set mode: Invalid argument vkms doesn't have modifiers support, set fb_modifiers_not_supported to bring the gdm back. Signed-off-by:
Yifan Zhang <yifan1.zhang@amd.com> Acked-by:
Guchun Chen <guchun.chen@amd.com> Reviewed-by:
Tim Huang <Tim.Huang@amd.com> Signed-off-by:
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Rodrigo Siqueira authored
Add basic kernel-doc that describes some of the struct and functions that are part of the DC commit sequence.. Tested-by:
Aurabindo Pillai <Aurabindo.Pillai@amd.com> Acked-by:
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Rodrigo Siqueira authored
Add kernel-doc to some important elements from DC struct that might help to understand DC sequence. Tested-by:
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Rodrigo Siqueira authored
Add kernel-doc to some of the ODM-related functions. Tested-by:
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Rodrigo Siqueira authored
Add a kernel-doc to the DE-Tile function hook. Tested-by:
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Rodrigo Siqueira authored
This commit adds extra documentation for elements related to FAMs. Tested-by:
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Ma Hanghong authored
[Why] For FreeSync HDR, native color space flag in AMD VSIF(BT.709) should be used when intepreting content and color space flag in VSC or AVI infoFrame should be ignored. However, it turned out some userspace application still use color flag in VSC or AVI infoFrame which is incorrect. [How] Transfer function is used when building the VSC and AVI infoFrame. Set colorimetry to BT.709 when all the following match: 1. Pixel format is YCbCr; 2. In FreeSync 2 HDR, color is COLOR_SPACE_2020_YCBCR; 3. Transfer function is TRANSFER_FUNC_GAMMA_22; Tested-by:
Krunoslav Kovac <Krunoslav.Kovac@amd.com> Acked-by:
Ma Hanghong <hanghong.ma@amd.com> Signed-off-by:
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zhikzhai authored
[WHY] Now dynamic ODM will now be disabled when MPO is required safe transitions to avoid underflow, but we are triggering the way of minimal transition too often. Commit state of dc with no check will do pipeline setup which may re-initialize the component with no need such as audio. [HOW] Just do the minimal transition when all of pipes are in use, otherwise return true to skip. Tested-by:
Dillon Varone <Dillon.Varone@amd.com> Acked-by:
zhikzhai <zhikai.zhai@amd.com> Signed-off-by:
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Haiyi Zhou authored
[WHY] Skipping vblank during global sync update request can result in underflow on certain displays. [HOW] Roll back to the previous behavior where DC waits for vblank during pipe programming. Fixes: 5d3e1442 ("drm/amd/display: do not wait for vblank during pipe programming") Tested-by:
Martin Leung <Martin.Leung@amd.com> Acked-by:
Haiyi Zhou <Haiyi.Zhou@amd.com> Signed-off-by:
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Aric Cyr authored
Apply SDR visual confirm to RGB10 and FP16 formats as well when needed. Tested-by:
Jun Lei <Jun.Lei@amd.com> Acked-by:
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Max Tseng authored
Missing send cursor_rect width & Height into DMUB. PSR-SU would use these information. But missing these assignment in last refactor commit Tested-by:
Anthony Koo <Anthony.Koo@amd.com> Acked-by:
Max Tseng <max.tseng@amd.com> Signed-off-by:
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Alvin Lee authored
Missed enabling timing sync on DCN32 because DCN32 has a different DML param. Tested-by:
Alvin Lee <Alvin.Lee2@amd.com> Signed-off-by:
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Bhawanpreet Lakha authored
[Why] On some linux based OS, the hotplug->HDCP start takes longer than 4seconds (by ~100ms) This is due to the HDCP delay (3 sec) so we only have 1 second to hotplug->stream enablement, which is not enough for certain OS configs. [How] Change the Delay to 0 seconds. From testing it seems like 0 Seconds can pass 1.x and 2.x compliances Tested-by:
Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by:
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Alvin Lee authored
Optimization caused unexpected regression, so remove for now. Tested-by:
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Dillon Varone authored
[Why] Cannot report 0 memclk levels even when SMU does not provide any. [How] When memclk levels reported by SMU is 0, set levels to 1. Tested-by:
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Dillon Varone authored
Update DF related latencies based on new measurements. Tested-by:
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Aric Cyr authored
DC version 3.2.208 brings along the following: * Add more kernel doc * Enable secure display on DCN21 * Limit dcn32 to 1950Mhz display clock * PSR code refactor * Rework audio stream sequence * Generic bug fixes Tested-by:
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Anthony Koo authored
Add a simple documentation in the dmub_cmd. Tested-by:
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Jun Lei authored
[why] Hardware team recommends we limit dispclock to 1950Mhz for all DCN3.2.x [how] Limit to 1950 when initializing clocks. Tested-by:
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Alan Liu authored
[Why] reuse struct rect rather than adding a new struct. [How] - Userspace keeps inputting x_start, y_start, x_end, y_end - We translate data to x, y, width, height in code flow to store - translate back to x_start, y_start, x_end, y_end before programming HW Tested-by:
Wayne Lin <Wayne.Lin@amd.com> Acked-by:
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Alan Liu authored
[Why] Porting secure display feature from DCN10 to DCN21. Support single display for now and will extend to multiple displays. [How] - use workqueue to offload works for dmub or dmcu firmware - after receiving ROI update from userspace, set skip_frame_cnt to 1 - refactor amdgpu_dm_crtc_handle_crc_window_irq() - disable PSR before activating secure_display on a crtc - check if secure_display is activated before enabling psr - only work for single display for now. Tested-by:
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Fangzhi Zuo authored
Ignore cable ID for DP2 receivers that does not support the feature. Tested-by:
Roman Li <Roman.Li@amd.com> Acked-by:
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Leo Chen authored
dcn314 has 4 DSC - conflicted hardware document updated and confirmed. Tested-by:
Charlene Liu <Charlene.Liu@amd.com> Acked-by:
Leo Chen <sancchen@amd.com> Signed-off-by:
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- 24 Oct, 2022 3 commits
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Joaquín Ignacio Aramendía authored
This file was split in commit 5d945cbc ("drm/amd/display: Create a file dedicated to planes") and the logic in dm_plane_format_mod_supported() function got changed by a switch logic. That change broke drm_plane modifiers setting on series 5000 APUs (tested on OXP mini AMD 5800U and HP Dev One 5850U PRO) leading to Gamescope not working as reported on GitHub[1] To reproduce the issue, enter a TTY and run: $ gamescope -- vkcube With said commit applied it will abort. This one restores the old logic, fixing the issue that affects Gamescope. [1](https://github.com/Plagman/gamescope/issues/624) Cc: <stable@vger.kernel.org> # 6.0.x Signed-off-by:
Joaquín Ignacio Aramendía <samsagax@gmail.com> Reviewed-by:
Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Signed-off-by:
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wangjianli authored
Delete the redundant word 'the'. Signed-off-by:
wangjianli <wangjianli@cdjrlc.com> Signed-off-by:
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wangjianli authored
Delete the redundant word 'the'. Signed-off-by:
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