- 15 Jun, 2020 4 commits
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Chris Wilson authored
Just in case everything fails (like for example "missed interrupt syndrome" on Sandybridge), always flush the submission tasklet from the heartbeat. This papers over such issues, but will still appear as a second long glitch, and prevents us from detecting it unless we happen to be performing a timed test. v2: We rely on flush_submission() synchronizing with the tasklet on another CPU. Signed-off-by:
Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by:
Mika Kuoppala <mika.kuoppala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200615165013.22973-3-chris@chris-wilson.co.uk
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Chris Wilson authored
If the engine dies after a reset, and so we fail to submit a request but need to be interrupted by the CI runner, dump the engine state. Signed-off-by:
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Chris Wilson authored
Since the heartbeat may cause a preemption event, disable it over the preemption suppression tests. Signed-off-by:
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Imre Deak authored
Atm, hotplug interrupts on TypeC ports are left enabled after detecting an interrupt storm, fix this. Reported-by:
Kunal Joshi <kunal1.joshi@intel.com> References: https://gitlab.freedesktop.org/drm/intel/-/issues/351 Bugzilla: https://gitlab.freedesktop.org/drm/intel/-/issues/1964 Cc: Kunal Joshi <kunal1.joshi@intel.com> Cc: stable@vger.kernel.org Signed-off-by:
Imre Deak <imre.deak@intel.com> Reviewed-by:
Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200612121731.19596-1-imre.deak@intel.com
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- 13 Jun, 2020 3 commits
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Chris Wilson authored
gen3 does not fully flush MI stores to memory on MI_FLUSH, such that a subsequent read from e.g. the sampler can bypass the store and read the stale value from memory. This is a serious issue when we are using MI stores to rewrite the batches for relocation, as it means that the batch is reading from random user/kernel memory. While it is particularly sensitive [and detectable] for relocations, reading stale data at any time is a worry. Having started with a small number of delaying stores and doubling until no more incoherency was seen over a few hours (with and without background memory pressure), 32 was the magic number. Note that it definitely doesn't fix the issue, merely adds a long delay between requests, sufficient to mostly hide the problem, enough to raise the mtbf to several hours. This is merely a stop gap. v2: Follow more closer with the gen5 w/a and include some post-invalidate flushes as well. Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/2018 References: a889580c ("drm/i915: Flush GPU relocs harder for gen3") Signed-off-by:
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Chris Wilson authored
Reduce the smoke depth by trimming the number of contexts, repetitions and wait times. This is in preparation for a less greedy scheduler that tries to be fair across contexts, resulting in a great many more context switches. A thousand context switches may be 50-100ms, causing us to timeout as the HW is not fast enough to complete the deep smoketests. Signed-off-by:
Andi Shyti <andi.shyti@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200607222108.14401-5-chris@chris-wilson.co.uk
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Chris Wilson authored
Since the process_csb() does not require us to hold the engine->active.lock, we can move the opportunistic flush before direction submission to outside of the lock. Signed-off-by:
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- 12 Jun, 2020 2 commits
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Chris Wilson authored
If we find ourselves trying to reuse a misplaced but active vma, we currently try to discard it to avoid having to wait to unbind it (upsetting the current user fo the vma). An alternative to marking it as a dicarded vma and keeping it in both the obj->vma.list and obj->vma.tree, is to simply remove it from the lookup rbtree. While it remains in the list of vma, it will be unbound under eviction pressure and freed along with the object. We will never reuse it again for new instances. As before, with no pruning, the list may continually grow, but eventually we will have the most constrained version of the ggtt view that meets all requirements -- so the list of vma should not grow without bound. Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/2012 Fixes: 9bdcaa5e ("drm/i915: Discard a misplaced GGTT vma") Signed-off-by:
Matthew Auld <matthew.auld@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200611180421.23262-1-chris@chris-wilson.co.uk
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Vandita Kulkarni authored
For all ddi, encoder->type holds output type as ddi, assigning it to individual o/p types is no more valid. Fixes: 362bfb99 ("drm/i915/tgl: Add DKL PHY vswing table for HDMI") v2: Rebase, no functional change. Signed-off-by:
Vandita Kulkarni <vandita.kulkarni@intel.com> Reviewed-by:
Uma Shankar <uma.shankar@intel.com> Signed-off-by:
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- 11 Jun, 2020 10 commits
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Chris Wilson authored
Rescue the GT workarounds from being buried inside init_clock_gating so that we remember to apply them after a GT reset, and that they are included in our verification that the workarounds are applied. Signed-off-by:
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Chris Wilson authored
Rescue the GT workarounds from being buried inside init_clock_gating so that we remember to apply them after a GT reset, and that they are included in our verification that the workarounds are applied. Signed-off-by:
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Chris Wilson authored
Rescue the GT workarounds from being buried inside init_clock_gating so that we remember to apply them after a GT reset, and that they are included in our verification that the workarounds are applied. Signed-off-by:
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Chris Wilson authored
Rescue the GT workarounds from being buried inside init_clock_gating so that we remember to apply them after a GT reset, and that they are included in our verification that the workarounds are applied. Signed-off-by:
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Chris Wilson authored
Rescue the GT workarounds from being buried inside init_clock_gating so that we remember to apply them after a GT reset, and that they are included in our verification that the workarounds are applied. Signed-off-by:
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Chris Wilson authored
Rescue the GT workarounds from being buried inside init_clock_gating so that we remember to apply them after a GT reset, and that they are included in our verification that the workarounds are applied. v2: Leave HSW_SCRATCH to set an explicit value, not or in our disable bit. Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/2011Signed-off-by:
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Chris Wilson authored
With the removal of the internal wait-priority boosting, we can also remove the selftest to ensure that those waits were being suppressed from causing preemptions. Signed-off-by:
Tvrtko Ursulin <tvrtko.ursulin@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200607222108.14401-4-chris@chris-wilson.co.uk
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Imre Deak authored
Currently MST on a port can get enabled/disabled from the hotplug work and get disabled from the short pulse work in a racy way. Fix this by relying on the MST state checking in the hotplug work and just schedule a hotplug work from the short pulse handler if some problem happened during the MST interrupt handling. This removes the explicit MST disabling in case of an AUX failure, but if AUX fails, then probably the detection will also fail during the scheduled hotplug work and it's not guaranteed that we'll see intermittent errors anyway. While at it also simplify the error checking of the MST interrupt handler. v2: - Convert intel_dp_check_mst_status() to return bool. (Ville) - Change the intel_dp->is_mst check to an assert, since after this patch the condition can't change after we checked it previously. - Document the return value from intel_dp_check_mst_status(). v3: - Remove the intel_dp->is_mst check from intel_dp_check_mst_status(). There is no point in checking the same condition twice, even though there is a chance that the hotplug work running concurrently changes it. Cc: José Roberto de Souza <jose.souza@intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by:
José Roberto de Souza <jose.souza@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200605094801.17709-1-imre.deak@intel.com
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Imre Deak authored
DSC is not supported on DP MST streams so just don't add this entry for MST connectors. This also fixes an OOPS, caused by the encoder->digport cast, which is not valid for MST encoders. v2: - Check encoder, which is unset for an MST connector, before it gets enabled. v3: - Just don't add this debugfs file for MST connectors. (Ville) Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by:
Manasi Navare <manasi.d.navare@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200609184140.4937-1-imre.deak@intel.com
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Imre Deak authored
According to BSpec the Data Island Packet should be disabled after disabling the transcoder, but before the transcoder clock select is set to none. On an ICL RVP, daisy-chained MST config not following this leads to a hang with the following MCE when disabling the output: [ 870.948739] mce: [Hardware Error]: CPU 0: Machine Check Exception: 5 Bank 6: ba00000011000402 [ 871.019212] mce: [Hardware Error]: RIP !INEXACT! 10:<ffffffff81aca652> {poll_idle+0x92/0xb0} [ 871.019212] mce: [Hardware Error]: TSC 135a261fe61 [ 871.019212] mce: [Hardware Error]: PROCESSOR 0:706e5 TIME 1591739604 SOCKET 0 APIC 0 microcode 20 [ 871.019212] mce: [Hardware Error]: Run the above through 'mcelog --ascii' [ 871.019212] mce: [Hardware Error]: Machine check: Processor context corrupt [ 871.019212] Kernel panic - not syncing: Fatal machine check [ 871.019212] Kernel Offset: disabled Bspec: 4287 Fixes: fa37a213 ("drm/i915: Stop sending DP SDPs on ddi disable") Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com> Cc: Uma Shankar <uma.shankar@intel.com> Signed-off-by:
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- 10 Jun, 2020 4 commits
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Chris Wilson authored
This may be useful to identify contexts that are running even though they are supposed to be closed or banned. Signed-off-by:
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Chris Wilson authored
We have a test case to exercise resetting an engine while the other engines are busy, all the TEST_SELF adds on top is that the target engine also has background activity. In this case it is useful to first test resetting the engine while there is background activity, as a separate flag from exercising all others. Signed-off-by:
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Chris Wilson authored
In commit 5ba32c7b ("drm/i915/execlists: Always force a context reload when rewinding RING_TAIL"), we placed the check for rewinding a context on actually submitting the next request in that context. This was so that we only had to check once, and could do so with precision avoiding as many forced restores as possible. For example, to ensure that we can resubmit the same request a couple of times, we include a small wa_tail such that on the next submission, the ring->tail will appear to move forwards when resubmitting the same request. This is very common as it will happen for every lite-restore to fill the second port after a context switch. However, intel_ring_direction() is limited in precision to movements of upto half the ring size. The consequence being that if we tried to unwind many requests, we could exceed half the ring and flip the sense of the direction, so missing a force restore. As no request can be greater than half the ring (i.e. 2048 bytes in the smallest case), we can check for rollback incrementally. As we check against the tail that would be submitted, we do not lose any sensitivity and allow lite restores for the simple case. We still need to double check upon submitting the context, to allow for multiple preemptions and resubmissions. Fixes: 5ba32c7b ("drm/i915/execlists: Always force a context reload when rewinding RING_TAIL") Signed-off-by:
Bruce Chang <yu.bruce.chang@intel.com> Reviewed-by:
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Khaled Almahallawy authored
Setting ln0 similar to ln1 Fixes: 3b51be4e ("drm/i915/tc: Update DP_MODE programming") Cc: <stable@vger.kernel.org> # v5.5+ Signed-off-by:
Khaled Almahallawy <khaled.almahallawy@intel.com> Reviewed-by:
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- 09 Jun, 2020 3 commits
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Aditya Swarup authored
RKL doesn't have DSI outputs, so we shouldn't try to read out the DSI transcoder registers. v2(MattR): - Just set the 'extra panel mask' to edp | dsi0 | dsi1 and then mask against the platform's cpu_transcoder_mask to filter out the ones that don't exist on a given platform. (Ville) v3(MattR): - Only include DSI transcoders on gen11+ again. (Ville) - Use for_each_cpu_transcoder_masked() for loop. (Ville) Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by:
Aditya Swarup <aditya.swarup@intel.com> Signed-off-by:
Matt Roper <matthew.d.roper@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200606025740.3308880-5-matthew.d.roper@intel.comReviewed-by:
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Matt Roper authored
HPD pin handling for RKL+TGP is a special case; we effectively select the HPD pin based on the DDI (A,B,D,E) rather than the PHY (A,B,C,D). This differs from the regular behavior of RKL+CMP (and also TGL+TGP). v2: - Rather than providing a custom hpd_pin mapping table, just assign encoder->hpd_pin in a custom manner for this setup. (Ville) Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by:
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Matt Roper authored
Rocket Lake uses the same 'abox0' mechanism to handle pixel data transfers from memory that gen11 platforms used, rather than the abox1/abox2 interfaces used by TGL/DG1. For the most part this is a hardware implementation detail that's transparent to driver software, but we do have to program a couple of tuning registers (MBUS_ABOX_CTL and BW_BUDDY registers) according to which ABOX instances are used by a platform. Let's track the platform's ABOX usage in the device info structure and use that to determine which instances of these registers to program. As an exception to this rule is that even though TGL/DG1 use ABOX1+ABOX2 for data transfers, we're still directed to program the ABOX_CTL register for ABOX0; so we'll handle that as a special case. v2: - Store the mask of platform-specific abox registers in the device info structure. - Add a TLB_REQ_TIMER() helper macro. (Aditya) v3: - Squash ABOX and BW_BUDDY patches together and use a single mask for both of them, plus a special-case for programming the ABOX0 instance on all gen12. (Ville) Bspec: 50096 Bspec: 49218 Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Aditya Swarup <aditya.swarup@intel.com> Signed-off-by:
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- 08 Jun, 2020 3 commits
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Chris Wilson authored
In some of our hangtests, we try to reset an active engine while it is spinning inside the recursive spinner. However, we also try to flood the engine with requests that preempt the hang, and so should disable the preemption to be sure that we reset the right request. Signed-off-by:
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Tvrtko Ursulin authored
Sentinels are supposed to be last requests in the elsp queue, not the only one, so adjust the assert accordingly. Signed-off-by:
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Stanislav Lisovskiy authored
This reverts commit 82ea174d. Unfortunately according to our recent findings there is still some unidentified factor, requiring CDCLK to be set higher - otherwise we still get underruns on some multipipe configurations, despite CDCLK being set according to BSpec formula. So getting again back into debug mode to indentify the cause, meanwhile setting CDCLK=Pixel rate back in order to remove regression in 10% of the cases due to FIFO underruns. Signed-off-by:
Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> Fixes: cd191546 ("drm/i915: Adjust CDCLK accordingly to our DBuf bw needs") Signed-off-by:
Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200608065552.21728-1-stanislav.lisovskiy@intel.com
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- 07 Jun, 2020 1 commit
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Gwan-gyeong Mun authored
The IO buffer Wake and Fast Wake bit size and value have been changed from Gen12+. It programs the default value of IO buffer Wake and Fast Wake on Gen12+. It adds definitions of IO buffer Wake and Fast Wake for pre Gen12 and Gen12+. And it aligns PSR2 definition macros. v2: Fix macro definitions. (José) v3: Addressed review comments from José - Add missing default values of IO_BUFFER_WAKE and FAST_WAKE for GEN9+ - Change a style of macro naming in order to use lines as input. - Update Todo comments. v4: Add parentheses to macros to avoid precedence issues. Cc: José Roberto de Souza <jose.souza@intel.com> Signed-off-by:
Gwan-gyeong Mun <gwan-gyeong.mun@intel.com> Reviewed-by:
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- 06 Jun, 2020 1 commit
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Matt Roper authored
We accidentally dropped matching for DVO_PORT_DPE from the VBT mapping table when we refactored the function. Restore it. Fixes: 4628142a ("drm/i915/rkl: provide port/phy mapping for vbt") Cc: Lucas De Marchi <lucas.demarchi@intel.com> Cc: Matt Roper <matthew.d.roper@intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by:
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- 05 Jun, 2020 9 commits
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Chris Wilson authored
Unused as of commit 9e0f9464 ("drm/i915/gem: Async GPU relocations only"), but left behind. >> drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c:933:21: error: unused function 'unmask_page' [-Werror,-Wunused-function] static inline void *unmask_page(unsigned long p) ^ >> drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c:938:28: error: unused function 'unmask_flags' [-Werror,-Wunused-function] static inline unsigned int unmask_flags(unsigned long p) ^ >> drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c:945:33: error: unused function 'cache_to_ggtt' [-Werror,-Wunused-function] static inline struct i915_ggtt *cache_to_ggtt(struct reloc_cache *cache) Reported-by:
kernel test robot <lkp@intel.com> Signed-off-by:
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Chris Wilson authored
As a last minute addition, I added an assertion to make sure that the new i915_vma view would be equal to the discard. However, the positive encouragement from CI only goes to show that we rarely take this path, and it wasn't until the post-merge run did we hit the assert -- because it compared the wrong view. Fixup the copy'n'paste error and compare against both the old view and the expected new view. Fixes: 9bdcaa5e ("drm/i915: Discard a misplaced GGTT vma") Signed-off-by:
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Chris Wilson authored
Across the many users of the GGTT vma (internal objects, mmapings, display etc), we may end up with conflicting requirements for the placement. Currently, we try to resolve the conflict by unbinding the vma and rebinding it to match the new constraints; over time we will end up with a GGTT that matches the most strict constraints over all concurrent users. However, this causes a problem if the vma is currently in use as we must wait until it is idle before moving it. But there is no restriction on the number of views we may use (apart from the limited size of the GGTT itself), and so if the active vma does not meet our requirements, try and build a new one! Signed-off-by:
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Chris Wilson authored
We may choose not to submit for a number of reasons, yet not fill both ELSP. In which case we must start timeslicing (there will be no ACK event on which to hook the start) if the queue would benefit from the currently active context being evicted. Signed-off-by:
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Chris Wilson authored
If we only submit the first port, leaving the second empty yet have ready requests pending in the queue, use that to set the timeslicing priority (i.e. the priority at which we will decided to enabling timeslicing and evict the currently active context if the queue is of equal priority after its quantum expired). Signed-off-by:
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Chris Wilson authored
Add engine->fw_domain/active to the pretty printer for debug dumps and debugfs. Signed-off-by:
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Kees Cook authored
This has no code changes, but the typo is clearly getting copy/pasted, so better to avoid this now and fix the typo. IS_ENABLED() takes full names, and must have the "CONFIG_" prefix. Reported-by:
Joe Perches <joe@perches.com> Link: https://lore.kernel.org/lkml/b08611018fdb6d88757c6008a5c02fa0e07b32fb.camel@perches.comSigned-off-by:
Kees Cook <keescook@chromium.org> Reviewed-by:
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Chris Wilson authored
Reduce the 3 relocation paths down to the single path that accommodates all. The primary motivation for this is to guard the relocations with a natural fence (derived from the i915_request used to write the relocation from the GPU). The tradeoff in using async gpu relocations is that it increases latency over using direct CPU relocations, for the cases where the target is idle and accessible by the CPU. The benefit is greatly reduced lock contention and improved concurrency by pipelining. Note that forcing the async gpu relocations does reveal a few issues they have. Firstly, is that they are visible as writes to gem_busy, causing to mark some buffers are being to written to by the GPU even though userspace only reads. Secondly is that, in combination with the cmdparser, they can cause priority inversions. This should be the case where the work is being put into a common workqueue losing our priority information and so being executed in FIFO from the worker, denying us the opportunity to reorder the requests afterwards. Signed-off-by:
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José Roberto de Souza authored
This parameter is meant to be used when PSR issues are found as some issues in the past was due wrong values set in VBT so this would be a quick and easy way to ask users or for us to check if the issue is due VBT values. Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com> Signed-off-by:
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