- 17 Jul, 2022 4 commits
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Johan Hovold authored
Three SoCs did not follow the interrupt order specified by the USB controller binding. While keeping the non-SuperSpeed interrupts together seems natural, reorder the interrupts to match the binding. Acked-by:
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by:
Johan Hovold <johan+linaro@kernel.org> [bjorn: Omitted sdx65 part from this patch] Signed-off-by:
Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220715070248.19078-5-johan+linaro@kernel.org
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Johan Hovold authored
Only one of the USB controllers supports SuperSpeed and have an SS PHY wakeup interrupt. Reorder the interrupts so that they match the updated binding which specifically has the optional interrupt last. Acked-by:
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Johan Hovold authored
The two single-port SC8280XP USB controllers do not have an hs_phy_irq interrupt. Instead they have a pwr_event interrupt which is distinct from the former and not yet supported by the driver. Fix the USB node interrupt names so that they match the devicetree binding. Also fix the pwr_event interrupt of the second controller which should be 811 as noticed by Andrew Halaney. Fixes: 152d1faf ("arm64: dts: qcom: add SC8280XP platform") Reviewed-by:
Andrew Halaney <ahalaney@redhat.com> Acked-by:
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Johan Hovold authored
Fix the USB controller clock order and naming so that they match the devicetree binding. Note that the driver currently simply enables all clocks in the order that they are specified in the devicetree. Reordering the clocks as per the binding means that the only explicit ordering constraint found in the vendor driver, that cfg_noc should be enabled before the core_clk, is now honoured. Fixes: 152d1faf ("arm64: dts: qcom: add SC8280XP platform") Signed-off-by:
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- 16 Jul, 2022 19 commits
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Johan Hovold authored
Fix the usb_1 SS PHY interrupt, which was mistakingly replaced with one of the usb_2 PHY interrupts. Signed-off-by:
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Manivannan Sadhasivam authored
PPI interrupt should be 7 for the PMU. Cc: Johan Hovold <johan+linaro@kernel.org> Fixes: 152d1faf ("arm64: dts: qcom: add SC8280XP platform") Reported-by:
Steve Capper <Steve.Capper@arm.com> Signed-off-by:
Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Reviewed-by:
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Parikshit Pareek authored
There has been wrong values introduced for context interrupt for smu node apps_smmu. Fix those ones with due correction. Fixes: 152d1faf ("arm64: dts: qcom: add SC8280XP platform") Signed-off-by:
Parikshit Pareek <quic_ppareek@quicinc.com> Signed-off-by:
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Sumit Garg authored
Currently the DT for QCS404 SoC has setup for 2 USB2 PHYs with one each assigned to USB3 controller and USB2 controller. This assignment is incorrect which only works by luck: as when each USB HCI comes up it configures the *other* controllers PHY which is enough to make them happy. If, for any reason, we were to disable one of the controllers then both would stop working. This was a difficult inconsistency to be caught which was found while trying to enable USB support in u-boot. So with all the required drivers ported to u-boot, I couldn't get the same USB storage device enumerated in u-boot which was being enumerated fine by the kernel. The root cause of the problem came out to be that I wasn't enabling USB2 PHY: "usb2_phy_prim" in u-boot. Then I realised that via simply disabling the same USB2 PHY currently assigned to USB2 host controller in the kernel disabled enumeration for USB3 host controller as well. So fix this inconsistency by correctly assigning USB2 PHYs. Fixes: 9375e7d7 ("arm64: dts: qcom: qcs404: Add USB devices and PHYs") Signed-off-by:
Sumit Garg <sumit.garg@linaro.org> Reviewed-by:
Daniel Thompson <daniel.thompson@linaro.org> Signed-off-by:
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Dmitry Baryshkov authored
The eDP node includes two clocks which are used by the eDP PHY rather than eDP controller itself. Drop these clocks to remove extra difference between eDP and DP controllers. Suggested-by:
Stephen Boyd <swboyd@chromium.org> Signed-off-by:
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by:
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Dmitry Baryshkov authored
Drop #address/#size-cells from eDP device node. For eDP the panels are not described directly under the controller node. They are either present under aux-bus child node, or they are declared separately (e.g. in a /soc node). Reviewed-by:
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Dmitry Baryshkov authored
Drop #clock-cells from DP device node. It is a leftover from the times before splitting the deviice into controller and PHY devices. Now the clocks are provided by the PHY, while the controller doesn't provide any clocks. Reviewed-by:
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Dmitry Baryshkov authored
Follow the schema for the DP controller and declare 5 register regions instead of using a single region for all the registers. Note, this extends the dts by adding p1 region to the DP node (to be used for DP MST). Signed-off-by:
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Dmitry Baryshkov authored
Drop #clock-cells from DP device node. It is a leftover from the times before splitting the device into controller and PHY devices. Now the clocks are provided by the PHY, while the controller doesn't provide any clocks. Reviewed-by:
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Dmitry Baryshkov authored
Follow the schema for the DP controller and declare 5 register regions instead of using a single region for all the registers. Note, this extends the dts by adding p1 region to the DP node (to be used for DP MST). Signed-off-by:
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Srinivasa Rao Mandadapu authored
Move wcd specific pin conf to common file to support various herbronie variant boards and to avoid duplicate nodes in dts files. Signed-off-by:
Srinivasa Rao Mandadapu <quic_srivasam@quicinc.com> Reviewed-by:
Douglas Anderson <dianders@chromium.org> Signed-off-by:
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Marijn Suijten authored
These voltages are not a multiple of the given step-size 8000 (with base voltage 1664000) in pm8998_pldo, resulting in PLDO regulators l18 and l22 failing to validate and in turn not probing the rpm-pm8998-regulator driver: l18: unsupportable voltage constraints 2856000-2848000uV qcom_rpm_smd_regulator rpm-glink:rpm-requests:pm8998-regulators: l18: devm_regulator_register() failed, ret=-22 Round the voltages down for the sake of erring on the safe side, leaving a comment in place to document this discrepancy wrt downstream sources. Fixes: 390883af ("arm64: dts: qcom: msm8998: Introduce support for Sony Yoshino platform") Reported-by:Konrad Dybcio <konrad.dybcio@somainline.org> Signed-off-by:
Marijn Suijten <marijn.suijten@somainline.org> Reviewed-by:
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Marijn Suijten authored
It seems the SM6350_CX definition was temporarily replaced with its literal value 0 in 1797e1c9 ("arm64: dts: qcom: sm6350: Add SDHCI1/2 nodes") to prevent a dependency on the qcom-rpmpd.h header patch being available prior to this DT patch being applied, similar to c23f1b77 ("arm64: dts: qcom: sm6125: Avoid using missing SM6125_VDDCX"). However, unlike the revert of that in the sm6125 tree the next merge window around in a90b8adf ("Revert "arm64: dts: qcom: sm6125: Avoid using missing SM6125_VDDCX""), this has not yet happened for sm6350: replace them back now that the definitions are definitely available. Signed-off-by:
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Robert Marko authored
Add interrupt-parent to the SoC DTSI to avoid duplicating it in each board DTS file. Remove interrupt-parent from existing board DTS files. Signed-off-by:
Robert Marko <robimarko@gmail.com> Signed-off-by:
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Robert Marko authored
Add #size-cells and #address-cells to the SoC DTSI to avoid duplicating the same properties in board DTS files. Remove the mentioned properties from current board DTS files. Signed-off-by:
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Dmitry Baryshkov authored
Rename DPU device node to display-controller@ae01000 to follow the DPU schema. Signed-off-by:
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Dmitry Baryshkov authored
Rename DPU device node to display-controller@ae01000 to follow the DPU schema. Signed-off-by:
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Dmitry Baryshkov authored
Rename DPU device node to display-controller@ae01000 to follow the DPU schema. Signed-off-by:
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Robert Marko authored
APCS now has support for providing the APSS clocks as the child device for IPQ8074. So, add the required DT node for it as it will later be used as the CPU clocksource. Signed-off-by:
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- 13 Jul, 2022 1 commit
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Bjorn Andersson authored
The timer node needs ranges specified to map the 1-cell children to the 2-cell address range used in /soc. This addition never made it into the patch that was posted and merged, so add it now. Fixes: 152d1faf ("arm64: dts: qcom: add SC8280XP platform") Signed-off-by:
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- 08 Jul, 2022 4 commits
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Johan Hovold authored
Fix up the DP PHY node which had the wrong unit address. Signed-off-by:
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Johan Hovold authored
Fix the usb_0 HS PHY reference clock which was mistakingly replaced with the first usb_2 PHY clock. Fixes: 152d1faf ("arm64: dts: qcom: add SC8280XP platform") Signed-off-by:
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Johan Hovold authored
The recent commit that dropped the PCIe PHY clock index failed to update the PCIe node reference. Fixes: 531c738f ("arm64: dts: qcom: sc7280: drop PCIe PHY clock index") Reported-by:
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Mauro Carvalho Chehab authored
This document was added without placing it at arm book. Fixes: 59228d3b ("dt-bindings: Document how Chromebooks with depthcharge boot") Signed-off-by:
Mauro Carvalho Chehab <mchehab@kernel.org> Reviewed-by:
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- 07 Jul, 2022 12 commits
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Johan Hovold authored
Clean up the PCIe PHY node by renaming the wrapper node and grouping the child node properties. Signed-off-by:
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Johan Hovold authored
Clean up the PCIe PHY nodes by using a non-empty ranges property. Signed-off-by:
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Johan Hovold authored
The QMP UFS PHY provides more than one symbol clock and would need an index to differentiate the clocks, but none of this is described by the binding currently. Drop the incorrect '#clock-cells' property for now. Signed-off-by:
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Johan Hovold authored
The QMP UFS PHY provides more than one symbol clock and would need an index to differentiate the clocks, but none of this is described by the binding currently. Drop the incorrect '#clock-cells' property for now. Signed-off-by:
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Johan Hovold authored
The QMP UFS PHY provides more than one symbol clock and would need an index to differentiate the clocks, but none of this is described by the binding currently. Drop the incorrect '#clock-cells' property for now. Signed-off-by:
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Johan Hovold authored
The QMP USB PHY provides a single clock so drop the redundant clock index. Signed-off-by:
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Johan Hovold authored
The QMP USB PHY provides a single clock so drop the redundant clock index. Signed-off-by:
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Johan Hovold authored
The QMP USB PHY provides a single clock so drop the redundant clock index. Signed-off-by:
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Johan Hovold authored
The QMP USB PHY provides a single clock so drop the redundant clock index. Signed-off-by:
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Johan Hovold authored
The QMP USB PHY provides a single clock so drop the redundant clock index. Signed-off-by:
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Johan Hovold authored
Add the missing '#clock-cells' properties to the PCIe QMP PHY nodes. Signed-off-by:
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Johan Hovold authored
The QMP PCIe PHY provides a single clock so drop the redundant clock index. Signed-off-by:
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