- 24 May, 2017 40 commits
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Nikola Pajkovsky authored
else branch is pointless if it's right at the end of function and use unlikely() on err path. Reviewed-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
Nikola Pajkovsky <npajkovsky@suse.cz> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Monk Liu authored
Signed-off-by:
Monk Liu <Monk.Liu@amd.com> Reviewed-by:
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Monk Liu authored
AI affected: CP/HW team requires KMD insert FRAME_CONTROL(end) after the last IB and before the fence of this DMAframe. this is to make sure the cache are flushed, and it's a must change no matter MCBP/SR-IOV or bare-metal case because new CP hw won't do the cache flush for each IB anymore, it just leaves it to KMD now. with this patch, certain MCBP hang issue when rendering vulkan/chained-ib are resolved. v2: drop gfx8 changes. gfx8 is not affected (Alex) Signed-off-by:
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Monk Liu authored
TMZ package will be used for VULKAN/CHAINED-IB MCBP Signed-off-by:
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Monk Liu authored
According to CP/hw team requirment, to support PAL/CHAINED-IB MCBP, kernel driver must guarantee DE_META must be inserted right prior to the work_load DE IB (with PREEMPT flag), there cannot be any non-work_load DE IB between-in DE_META and work_load DE IB. Signed-off-by:
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Monk Liu authored
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Monk Liu authored
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Frank Min authored
According to HW design, need to clean doorbell after setup MMSCH table. Signed-off-by:
Frank Min <Frank.Min@amd.com> Signed-off-by:
Xiangliang Yu <Xiangliang.Yu@amd.com> Reviewed-by:
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Xiangliang Yu authored
Change message to debug level as VI does. Signed-off-by:
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Xiangliang Yu authored
If psp version doesn't match asd version, asd loading will be failed. Add workaround to bypass it for sriov. Signed-off-by:
Daniel Wang <Daniel.Wang2@amd.com> Signed-off-by:
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Trigger Huang authored
On vega10, some hw finish operations should not be applied in SR-IOV case. This works as workaround to fix multi-VFs reboot/shutdown issues. Signed-off-by:
Trigger Huang <trigger.huang@amd.com> Reviewed-by:
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Monk Liu authored
1,this way we make those routines compatible with the sequence requirment for both Tonga and Vega10 2,ignore PSP hw init when doing TDR, because for SR-IOV device the ucode won't get lost after VF FLR, so no need to invoke PSP doing the ucode reloading again. v2: squash in ARRAY_SIZE fix Signed-off-by:
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Monk Liu authored
if sriov gpu reset is invoked by job timeout, it is run in a global work-queue which is very slow and better not call msleep ortherwise it takes long time to get back CPU. so make below changes: 1: Change msleep 1 to mdelay 5 2: Ignore the ack fail from pf after time out, because VF FLR will clear ack, sometime VF FLR is done prior to the beginning of poll_ack so we can ignore this ack TODO: Put job_timedout (and the following gpu reset) in a driver thread, instead of the global work_struct. Signed-off-by:
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Monk Liu authored
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Monk Liu authored
this is to prevent fence forever waiting if FLR occured during register accessing. v2: use define instead of hardcode for the timeout msec Signed-off-by:
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Alex Deucher authored
We need to make sure the various init sequences submitted to KIQ complete before testing the rings. Reviewed-by:
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Alex Deucher authored
Rather than magic numbers. Reviewed-by:
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Alex Deucher authored
Will be used in subsequent commits rather rather than magic numbers. Reviewed-by:
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Alex Deucher authored
To be consistent with gfx8. Reviewed-by:
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Alex Deucher authored
And properly synchronize them with the master during queue init. Reviewed-by:
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Shaoyun Liu authored
The usage of kiq should not depend on the virtualization. Signed-off-by:
Shaoyun Liu <Shaoyun.Liu@amd.com> Reviewed-by:
Andres Rodriquez <andresx7@gmail.com> Signed-off-by:
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Chunming Zhou authored
Interface to reserve a vmid for a specific process to add in shader debugging that requries a fixed vmid. Signed-off-by:
Chunming Zhou <David1.Zhou@amd.com> Reviewed-by:
Junwei Zhang <Jerry.Zhang@amd.com> Reviewed-by:
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Chunming Zhou authored
Implement the vmid reservation. v2: move sync waiting only when flush needs v3: fix racy v4: peek fence instead of get fence, and fix potential context starved. Signed-off-by:
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Chunming Zhou authored
Limit reserved vmids to 1 to avoid taking too many out of commission and starving the system. v2: move #define to amdgpu_vm.h v3: move reserved vmid counter to id_manager, and increase counter before allocating vmid v4: rename to reserved_vmid_num Signed-off-by:
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Chunming Zhou authored
add reserve/unreserve vmid funtions. Used to reserve vmids for certain shader debugging functionality that required a fixed vmid for the life of the debug. v3: only reserve vmid from gfxhub v4: fix racy condition Signed-off-by:
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Chunming Zhou authored
v2: rename dedicated_vmid to reserved_vmid Signed-off-by:
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Chunming Zhou authored
It will be used for reserving vmid for shader debugging that requires a fixed vmid. v2: fix warning (Alex) Signed-off-by:
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Trigger Huang authored
Support for MCBP/Virtualization in combination with chained IBs is formal released on firmware feature version #46. So enable it according to firmware feature version, otherwise, world switch will hang. Signed-off-by:
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Rex Zhu authored
Bug: SWDEV-117987: Always on CU mask broken for gfx7+ Signed-off-by:
Rex Zhu <Rex.Zhu@amd.com> Acked-by:
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Rex Zhu authored
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Xiangliang Yu authored
Change place of virt_init_setting function so that can cover the cg and pg flags configuration. Signed-off-by:
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Xiangliang Yu authored
GPU hypervisor cover all settings of CG and PG, so guest doesn't need to do anything. Bypass it. Signed-off-by:
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Christian König authored
Only per family registers are still used. Signed-off-by:
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Christian König authored
I couldn't figure out what this was original good for, but we don't use it any more. Signed-off-by:
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Rex Zhu authored
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Rex Zhu authored
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Xiaojie Yuan authored
Signed-off-by:
Xiaojie Yuan <Xiaojie.Yuan@amd.com> Reviewed-by:
Edward O'Callaghan <funfunctor@folklore1984.net> Reviewed-by:
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Xiaojie Yuan authored
v2: refine dce_v6_0_audio_endpt_wreg() and unify inconsistent method names v3: fix num_pins for tahiti, pitcairn, verde and oland Signed-off-by:
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Alex Deucher authored
I'm not sure if the order matters, but it seems like it makes more sense to set this after the range is programmed. v2: rebase (Alex) Signed-off-by: -
Rex Zhu authored
add set_doorbell functions for mec and cpg. Signed-off-by:
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