- 12 Jan, 2023 5 commits
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Arseniy Krasnov authored
This updates message bound test making it more complex. Instead of sending 1 bytes messages with one MSG_EOR bit, it sends messages of random length(one half of messages are smaller than page size, second half are bigger) with random number of MSG_EOR bits set. Receiver also don't know total number of messages. Signed-off-by:
Arseniy Krasnov <AVKrasnov@sberdevices.ru> Reviewed-by:
Stefano Garzarella <sgarzare@redhat.com> Signed-off-by:
Paolo Abeni <pabeni@redhat.com>
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Bobby Eshleman authored
This removes behaviour, where error code returned from any transport was always switched to ENOMEM. For example when user tries to send too big message via SEQPACKET socket, transport layers return EMSGSIZE, but this error code was always replaced with ENOMEM and returned to user. Signed-off-by:
Bobby Eshleman <bobby.eshleman@bytedance.com> Signed-off-by:
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Lorenzo Bianconi authored
Queue spinlock is currently held in mtk_wed_wo_queue_rx_clean and mtk_wed_wo_queue_refill routines for MTK Wireless Ethernet Dispatcher MCU rx queue. mtk_wed_wo_queue_refill() is running during initialization and in rx tasklet while mtk_wed_wo_queue_rx_clean() is running in mtk_wed_wo_hw_deinit() during hw de-init phase after rx tasklet has been disabled. Since mtk_wed_wo_queue_rx_clean and mtk_wed_wo_queue_refill routines can't run concurrently get rid of spinlock for mcu rx queue. Reviewed-by:
Alexander Duyck <alexanderduyck@fb.com> Signed-off-by:
Lorenzo Bianconi <lorenzo@kernel.org> Link: https://lore.kernel.org/r/36ec3b729542ea60898471d890796f745479ba32.1673342990.git.lorenzo@kernel.orgSigned-off-by:
Jakub Kicinski <kuba@kernel.org>
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Jakub Kicinski authored
The reference needs to keep the instance memory around, but also the instance lock must remain valid. Users will take the lock, check registration status and release the lock. mutex_destroy() etc. belong in the same place as the freeing of the memory. Unfortunately lockdep_unregister_key() sleeps so we need to switch the an rcu_work. Note that the problem is a bit hard to repro, because devlink_pernet_pre_exit() iterates over registered instances. AFAIU the instances must get devlink_free()d concurrently with the namespace getting deleted for the problem to occur. Reported-by: syzbot+d94d214ea473e218fc89@syzkaller.appspotmail.com Reported-by: syzbot+9f0dd863b87113935acf@syzkaller.appspotmail.com Fixes: 9053637e ("devlink: remove the registration guarantee of references") Reviewed-by:
Jiri Pirko <jiri@nvidia.com> Reviewed-by:
Jacob Keller <jacob.e.keller@intel.com> Link: https://lore.kernel.org/r/20230111042908.988199-1-kuba@kernel.orgSigned-off-by:
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Heiner Kallweit authored
There are still single reports of systems where ASPM incompatibilities cause tx timeouts. It's not clear whom to blame, so let's disable ASPM in case of a tx timeout. v2: - add one-time warning for informing the user Signed-off-by:
Heiner Kallweit <hkallweit1@gmail.com> Reviewed-by:
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- 11 Jan, 2023 25 commits
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Jakub Kicinski authored
Neil Armstrong says: ==================== dt-bindings: first batch of dt-schema conversions for Amlogic Meson bindings Batch conversion of the following bindings: [...] - mdio-mux-meson-g12a.txt ==================== Link: https://lore.kernel.org/r/20221117-b4-amlogic-bindings-convert-v2-0-36ad050bb625@linaro.orgSigned-off-by:
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Neil Armstrong authored
Convert MDIO bus multiplexer/glue of Amlogic G12a SoC family bindings to dt-schema. Reviewed-by:
Martin Blumenstingl <martin.blumenstingl@googlemail.com> Reviewed-by:
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by:
Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by:
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git://git.kernel.org/pub/scm/linux/kernel/git/saeed/linuxDavid S. Miller authored
mlx5-updates-2023-01-10 1) From Gal: Add debugfs entries for netdev nic driver - ktls, flow steering and hairpin info - useful for debug and performance analysis - e.g hairpin queue attributes, dump ktls tx pool size, etc 2) From Maher: Update shared buffer configuration on PFC commands 2.1) For every change of buffer's headroom, recalculate the size of shared buffer to be equal to "total_buffer_size" - "new_headroom_size". The new shared buffer size will be split in ratio of 3:1 between lossy and lossless pools, respectively. 2.2) For each port buffer change, count the number of lossless buffers. If there is only one lossless buffer, then set its lossless pool usage threshold to be infinite. Otherwise, if there is more than one lossless buffer, set a usage threshold for each lossless buffer. While at it, add more verbosity to debug prints when handling user commands, to assist in future debug. 3) From Tariq: Throttle high rate FW commands 4) From Shay: Properly initialize management PF 5) Various cleanup patches -
David S. Miller authored
Piergiorgio Beruto says: ==================== net: add PLCA RS support and onsemi NCN26000 This patchset adds support for getting/setting the Physical Layer Collision Avoidace (PLCA) Reconciliation Sublayer (RS) configuration and status on Ethernet PHYs that supports it. PLCA is a feature that provides improved media-access performance in terms of throughput, latency and fairness for multi-drop (P2MP) half-duplex PHYs. PLCA is defined in Clause 148 of the IEEE802.3 specifications as amended by 802.3cg-2019. Currently, PLCA is supported by the 10BASE-T1S single-pair Ethernet PHY defined in the same standard and related amendments. The OPEN Alliance SIG TC14 defines additional specifications for the 10BASE-T1S PHY, including a standard register map for PHYs that embeds the PLCA RS (see PLCA management registers at https://www.opensig.org/about/specifications/). The changes proposed herein add the appropriate ethtool netlink interface for configuring the PLCA RS on PHYs that supports it. A separate patchset further modifies the ethtool userspace program to show and modify the configuration/status of the PLCA RS. Additionally, this patchset adds support for the onsemi NCN26000 Industrial Ethernet 10BASE-T1S PHY that uses the newly added PLCA infrastructure. ==================== Signed-off-by:
David S. Miller <davem@davemloft.net>
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Piergiorgio Beruto authored
This patch adds support for the onsemi NCN26000 10BASE-T1S industrial Ethernet PHY. The driver supports Point-to-Multipoint operation without auto-negotiation and with link control handling. The PHY also features PLCA for improving performance in P2MP mode. Signed-off-by:
Piergiorgio Beruto <piergiorgio.beruto@gmail.com> Reviewed-by:
Andrew Lunn <andrew@lunn.ch> Signed-off-by:
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Piergiorgio Beruto authored
This patch adds support in phylib to read/write PLCA configuration for Ethernet PHYs that support the OPEN Alliance "10BASE-T1S PLCA Management Registers" specifications. These can be found at https://www.opensig.org/about/specifications/Signed-off-by:
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Piergiorgio Beruto authored
This patch adds the required connection between netlink ethtool and phylib to resolve PLCA get/set config and get status messages. Signed-off-by:
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Piergiorgio Beruto authored
This patch adds the link modes for the IEEE 802.3cg Clause 147 10BASE-T1S Ethernet PHY. According to the specifications, the 10BASE-T1S supports Point-To-Point Full-Duplex, Point-To-Point Half-Duplex and/or Point-To-Multipoint (AKA Multi-Drop) Half-Duplex operations. Signed-off-by:
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Piergiorgio Beruto authored
Add support for configuring the PLCA Reconciliation Sublayer on multi-drop PHYs that support IEEE802.3cg-2019 Clause 148 (e.g., 10BASE-T1S). This patch adds the appropriate netlink interface to ethtool. Signed-off-by:
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YueHaibing authored
'accel_tcp' is allocted by kvzalloc() now, which is a small chunk. Use kzalloc() directly instead of kvzalloc(). Signed-off-by:
YueHaibing <yuehaibing@huawei.com> Reviewed-by:
Tariq Toukan <tariqt@nvidia.com> Signed-off-by:
Saeed Mahameed <saeedm@nvidia.com>
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zhang songyi authored
Return value from mlx5dr_send_postsend_action() directly instead of taking this in another redundant variable. Signed-off-by:
zhang songyi <zhang.songyi@zte.com.cn> Reviewed-by:
Roi Dayan <roid@nvidia.com> Reviewed-by:
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Kees Cook authored
Zero-length arrays are deprecated[1]. Replace struct mlx5e_rx_wqe_cyc's "data" 0-length array with a flexible array. Detected with GCC 13, using -fstrict-flex-arrays=3: drivers/net/ethernet/mellanox/mlx5/core/en_main.c: In function 'mlx5e_alloc_rq': drivers/net/ethernet/mellanox/mlx5/core/en_main.c:827:42: warning: array subscript f is outside array bounds of 'struct mlx5_wqe_data_seg[0]' [-Warray-bounds=] 827 | wqe->data[f].byte_count = 0; | ~~~~~~~~~^~~ In file included from drivers/net/ethernet/mellanox/mlx5/core/en/tc_ct.h:11, from drivers/net/ethernet/mellanox/mlx5/core/eswitch.h:48, from drivers/net/ethernet/mellanox/mlx5/core/en_main.c:42: drivers/net/ethernet/mellanox/mlx5/core/en.h:250:39: note: while referencing 'data' 250 | struct mlx5_wqe_data_seg data[0]; | ^~~~ [1] https://www.kernel.org/doc/html/latest/process/deprecated.html#zero-length-and-one-element-arrays Cc: Saeed Mahameed <saeedm@nvidia.com> Cc: Leon Romanovsky <leon@kernel.org> Cc: "David S. Miller" <davem@davemloft.net> Cc: Eric Dumazet <edumazet@google.com> Cc: Jakub Kicinski <kuba@kernel.org> Cc: Paolo Abeni <pabeni@redhat.com> Cc: "Gustavo A. R. Silva" <gustavoars@kernel.org> Cc: netdev@vger.kernel.org Cc: linux-rdma@vger.kernel.org Signed-off-by:Kees Cook <keescook@chromium.org> Reviewed-by:
Gustavo A. R. Silva <gustavoars@kernel.org> Reviewed-by:
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Gustavo A. R. Silva authored
Zero-length arrays are deprecated[1] and we are moving towards adopting C99 flexible-array members instead. So, replace zero-length array declaration in struct mlx5e_flow_meter_aso_obj with flex-array member. This helps with the ongoing efforts to tighten the FORTIFY_SOURCE routines on memcpy() and help us make progress towards globally enabling -fstrict-flex-arrays=3 [2]. Link: https://www.kernel.org/doc/html/latest/process/deprecated.html#zero-length-and-one-element-arrays [1] Link: https://gcc.gnu.org/pipermail/gcc-patches/2022-October/602902.html [2] Link: https://github.com/KSPP/linux/issues/78Signed-off-by:
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Tariq Toukan authored
Certain connection-based device-offload protocols (like TLS) use per-connection HW objects to track the state, maintain the context, and perform the offload properly. Some of these objects are created, modified, and destroyed via FW commands. Under high connection rate, this type of FW commands might continuously populate all slots of the FW command interface and throttle it, while starving other critical control FW commands. Limit these throttle commands to using only up to a portion (half) of the FW command interface slots. FW commands maximal rate is not hit, and the same high rate is still reached when applying this limitation. Signed-off-by:
Moshe Shemesh <moshe@nvidia.com> Signed-off-by:
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Tariq Toukan authored
Introduce an opcode getter in the FW command interface, and use it. Initialize the entry's opcode field early in cmd_alloc_ent() and use it when possible. Signed-off-by:
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Shay Drory authored
Enable initialization of DPU Management PF, which is a new loopback PF designed for communication with BMC. For now Management PF doesn't support nor require most upper layer protocols so avoid them. Signed-off-by:
Shay Drory <shayd@nvidia.com> Reviewed-by:
Eran Ben Elisha <eranbe@nvidia.com> Reviewed-by:
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Gal Pressman authored
We refer to a TC NIC rule that involves forwarding as "hairpin". Hairpin queues are mlx5 hardware specific implementation for hardware forwarding of such packets. For debug purposes, introduce debugfs files which: * Expose the number of active hairpins * Dump the hairpin table * Allow control over the number and size of the hairpin queues instead of the hard-coded values. This allows us to get visibility of the feature in order to improve it for next generation hardware. Add debugfs files: fs/tc/hairpin_num_active fs/tc/hairpin_num_queues fs/tc/hairpin_queue_size fs/tc/hairpin_table_dump Note that the new values will only take effect on the next queues creation, it does not affect existing queues. Signed-off-by:
Gal Pressman <gal@nvidia.com> Reviewed-by:
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Gal Pressman authored
Add a debugfs directory for flow steering related information. The directory is currently empty, and will hold the 'tc' subdirectory in a downstream patch. Signed-off-by:
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Gal Pressman authored
In preparation for downstream work to expose hairpin queues parameters, introduce a hairpin parameters struct as part of the tc structure. Signed-off-by:
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Tariq Toukan authored
Add TLS debugfs to improve observability by exposing the size of the tls TX pool. To observe the size of the TX pool: $ cat /sys/kernel/debug/mlx5/<pci>/nic/tls/tx/pool_size Signed-off-by:
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Gal Pressman authored
Similar to the mlx5_core debugfs, lay the groundwork for mlx5e debugfs files under /sys/kernel/debug/mlx5/<pci>/nic/.. Signed-off-by:
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Maher Sanalla authored
Currently, the user can modify device's receive buffer size, modify the mapping between QoS priority groups to buffers and change the buffer state to become lossy/lossless via pfc command. However, the shared receive buffer pool alignments, as a result of such commands, is performed only when the shared buffer is in FW ownership. When a user changes the mapping of priority groups or buffer size, the shared buffer is moved to SW ownership. Therefore, for devices that support shared buffer, handle the shared buffer alignments in accordance to user's desired configurations. Meaning, the following will be performed: 1. For every change of buffer's headroom, recalculate the size of shared buffer to be equal to "total_buffer_size" - "new_headroom_size". The new shared buffer size will be split in ratio of 3:1 between lossy and lossless pools, respectively. 2. For each port buffer change, count the number of lossless buffers. If there is only one lossless buffer, then set its lossless pool usage threshold to be infinite. Otherwise, if there is more than one lossless buffer, set a usage threshold for each lossless buffer. While at it, add more verbosity to debug prints when handling user commands, to assist in future debug. Signed-off-by:
Maher Sanalla <msanalla@nvidia.com> Reviewed-by:
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Maher Sanalla authored
To allow users to configure shared receive buffer parameters through dcbnl callbacks, expose an API to query and modify SBPR and SBCM registers, which will be used in the upcoming patch. Signed-off-by:
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Maher Sanalla authored
Add the shared receive buffer management and configuration registers: 1. SBPR - Shared Buffer Pools Register 2. SBCM - Shared Buffer Class Management Register Signed-off-by:
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Dai Shixin authored
Fix a typo of "permision" which should be "permission". Signed-off-by:
Dai Shixin <dai.shixin@zte.com.cn> Signed-off-by:
Yang Yang <yang.yang29@zte.com.cn> Link: https://lore.kernel.org/r/202301091935262709751@zte.com.cnSigned-off-by:
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- 10 Jan, 2023 10 commits
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Jakub Kicinski authored
Michael Walle says: ==================== net: mdio: Start separating C22 and C45 This patch set starts the separation of C22 and C45 MDIO bus transactions at the API level to the MDIO Bus drivers. C45 read and write ops are added to the MDIO bus driver structure, and the MDIO core will try to use these ops if requested to perform a C45 transfer. If not available a fallback to the older API is made, to allow backwards compatibility until all drivers are converted. A few drivers are then converted to this new API. The core DSA patch was dropped for now as there is still an ongoing discussion. It will be picked up in a later series again. v2: https://lore.kernel.org/r/20221227-v6-2-rc1-c45-seperation-v2-0-ddb37710e5a7@walle.cc v1: https://lore.kernel.org/r/20220508153049.427227-1-andrew@lunn.ch ==================== Link: https://lore.kernel.org/r/20221227-v6-2-rc1-c45-seperation-v3-0-ade1deb438da@walle.ccSigned-off-by:
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Andrew Lunn authored
The global2 SMI MDIO bus driver can perform both C22 and C45 transfers. Create separate functions for each and register the C45 versions using the new API calls where appropriate. Update the SERDES code to make use of these new accessors. Signed-off-by:
Michael Walle <michael@walle.cc> Reviewed-by:
Vladimir Oltean <vladimir.oltean@nxp.com> Signed-off-by:
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Andrew Lunn authored
Some DSA devices pass through PHY access to the MDIO bus the switch is on. Add C45 versions of the current C22 helpers for nested accesses to MDIO busses, so that C22 and C45 can be separated in these DSA drivers. Signed-off-by:
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Andrew Lunn authored
The fec MDIO bus driver can perform both C22 and C45 transfers. Create separate functions for each and register the C45 versions using the new API calls where appropriate. Signed-off-by:
Wei Fang <wei.fang@nxp.com> Signed-off-by:
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Andrew Lunn authored
The xgmac MDIO bus driver can perform both C22 and C45 transfers. Create separate functions for each and register the C45 versions using the new API calls where appropriate. While at it, remove the misleading comment. According to Vladimir Oltean: - miimcom is a register accessed by fsl_pq_mdio.c, not by xgmac_mdio.c - "device dev" doesn't really refer to anything (maybe "dev_addr"). - I don't understand what is meant by the comment "All PHY configuration has to be done through the TSEC1 MIIM regs". Or rather said, I think I understand, but it is irrelevant to the driver for 2 reasons: * TSEC devices use the fsl_pq_mdio.c driver, not this one * It doesn't matter to this driver whose TSEC registers are used for MDIO access. The driver just works with the registers it's given, which is a concern for the device tree. - barring the above, the rest just describes the MDIO bus API, which is superfluous Signed-off-by: -
Andrew Lunn authored
The marvell MDIO driver supports two different hardware blocks. The XSMI block is C45 only. Convert this block to the new API, and only populate the c45 calls in the bus structure. Signed-off-by:
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Andrew Lunn authored
The bitbbanging bus driver can perform both C22 and C45 transfers. Create separate functions for each and register the C45 versions using the new driver API calls. The SH Ethernet driver places wrappers around these functions. In order to not break boards which might be using C45, add similar wrappers for C45 operations. Reviewed-by:
Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by:
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Andrew Lunn authored
Now that mdiobus_c45_addr() is only used within the MDIO code during fallback, move the function next to its only users. This function should not be used any more in drivers, the c45 helpers should be used in its place, so hiding it away will prevent any new users from being added. Signed-off-by:
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Andrew Lunn authored
When performing a C22 operation, check that the bus driver actually provides the methods, and return -EOPNOTSUPP if not. C45 only busses do exist, and in future their C22 methods will be NULL. Signed-off-by:
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Andrew Lunn authored
Now that C45 uses its own read/write methods, the validation performed when a bus is registers needs updating. All combinations of C22 and C45 are supported, but both read and write methods must be provided, read only busses are not supported etc. Signed-off-by:
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