1. 16 May, 2022 7 commits
    • David S. Miller's avatar
      Merge branch 'Renesas-RSZ-V2M-support' · 5cf15ce3
      David S. Miller authored
      Phil Edworthy says:
      
      ====================
      Add Renesas RZ/V2M Ethernet support
      
      The RZ/V2M Ethernet is very similar to R-Car Gen3 Ethernet-AVB, though
      some small parts are the same as R-Car Gen2.
      Other differences are:
      * It has separate data (DI), error (Line 1) and management (Line 2) irqs
        rather than one irq for all three.
      * Instead of using the High-speed peripheral bus clock for gPTP, it has
        a separate gPTP reference clock.
      
      v4:
       * Add clk_disable_unprepare() for gptp ref clk
      
      v3:
       * Really renamed irq_en_dis_regs to irq_en_dis this time
       * Modified ravb_ptp_extts() to use irq_en_dis
       * Added Reviewed-by tags
      
      v2:
       * Just net patches in this series
       * Instead of reusing ch22 and ch24 interrupt names, use the proper names
       * Renamed irq_en_dis_regs to irq_en_dis
       * Squashed use of GIC reg versus GIE/GID and got rid of separate gptp_ptm_gic feature.
       * Move err_mgmt_irqs code under multi_irqs
       * Minor editing of the commit msgs
      ====================
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      5cf15ce3
    • Phil Edworthy's avatar
      ravb: Add support for RZ/V2M · e1154be7
      Phil Edworthy authored
      RZ/V2M Ethernet is very similar to R-Car Gen3 Ethernet-AVB, though
      some small parts are the same as R-Car Gen2.
      Other differences to R-Car Gen3 and Gen2 are:
      * It has separate data (DI), error (Line 1) and management (Line 2) irqs
        rather than one irq for all three.
      * Instead of using the High-speed peripheral bus clock for gPTP, it has a
        separate gPTP reference clock.
      Signed-off-by: default avatarPhil Edworthy <phil.edworthy@renesas.com>
      Reviewed-by: default avatarBiju Das <biju.das.jz@bp.renesas.com>
      Reviewed-by: default avatarSergey Shtylyov <s.shtylyov@omp.ru>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      e1154be7
    • Phil Edworthy's avatar
      ravb: Use separate clock for gPTP · 72069a7b
      Phil Edworthy authored
      RZ/V2M has a separate gPTP reference clock that is used when the
      AVB-DMAC Mode Register (CCC) gPTP Clock Select (CSEL) bits are
      set to "01: High-speed peripheral bus clock".
      Therefore, add a feature that allows this clock to be used for
      gPTP.
      Signed-off-by: default avatarPhil Edworthy <phil.edworthy@renesas.com>
      Reviewed-by: default avatarBiju Das <biju.das.jz@bp.renesas.com>
      Reviewed-by: default avatarSergey Shtylyov <s.shtylyov@omp.ru>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      72069a7b
    • Phil Edworthy's avatar
      ravb: Support separate Line0 (Desc), Line1 (Err) and Line2 (Mgmt) irqs · b0265dcb
      Phil Edworthy authored
      R-Car has a combined interrupt line, ch22 = Line0_DiA | Line1_A | Line2_A.
      RZ/V2M has separate interrupt lines for each of these, so add a feature
      that allows the driver to get these interrupts and call the common handler.
      Signed-off-by: default avatarPhil Edworthy <phil.edworthy@renesas.com>
      Reviewed-by: default avatarBiju Das <biju.das.jz@bp.renesas.com>
      Reviewed-by: default avatarSergey Shtylyov <s.shtylyov@omp.ru>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      b0265dcb
    • Phil Edworthy's avatar
      ravb: Separate handling of irq enable/disable regs into feature · cb99badd
      Phil Edworthy authored
      Currently, when the HW has a single interrupt, the driver uses the
      GIC, TIC, RIC0 registers to enable and disable interrupts.
      When the HW has multiple interrupts, it uses the GIE, GID, TIE, TID,
      RIE0, RID0 registers.
      
      However, other devices, e.g. RZ/V2M, have multiple irqs and only have
      the GIC, TIC, RIC0 registers.
      Therefore, split this into a separate feature.
      Signed-off-by: default avatarPhil Edworthy <phil.edworthy@renesas.com>
      Reviewed-by: default avatarBiju Das <biju.das.jz@bp.renesas.com>
      Reviewed-by: default avatarSergey Shtylyov <s.shtylyov@omp.ru>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      cb99badd
    • Phil Edworthy's avatar
      dt-bindings: net: renesas,etheravb: Document RZ/V2M SoC · a7931ac1
      Phil Edworthy authored
      Document the Ethernet AVB IP found on RZ/V2M SoC.
      It includes the Ethernet controller (E-MAC) and Dedicated Direct memory
      access controller (DMAC) for transferring transmitted Ethernet frames
      to and received Ethernet frames from respective storage areas in the
      RAM at high speed.
      The AVB-DMAC is compliant with IEEE 802.1BA, IEEE 802.1AS timing and
      synchronization protocol, IEEE 802.1Qav real-time transfer, and the
      IEEE 802.1Qat stream reservation protocol.
      
      R-Car has a pair of combined interrupt lines:
       ch22 = Line0_DiA | Line1_A | Line2_A
       ch23 = Line0_DiB | Line1_B | Line2_B
      Line0 for descriptor interrupts (which we call dia and dib).
      Line1 for error related interrupts (which we call err_a and err_b).
      Line2 for management and gPTP related interrupts (mgmt_a and mgmt_b).
      
      RZ/V2M hardware has separate interrupt lines for each of these.
      
      It has 3 clocks; the main AXI clock, the AMBA CHI (Coherent Hub
      Interface) clock and a gPTP reference clock.
      Signed-off-by: default avatarPhil Edworthy <phil.edworthy@renesas.com>
      Reviewed-by: default avatarBiju Das <biju.das.jz@bp.renesas.com>
      Reviewed-by: default avatarSergey Shtylyov <s.shtylyov@omp.ru>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      a7931ac1
    • David S. Miller's avatar
      Merge git://git.kernel.org/pub/scm/linux/kernel/git/netfilter/nf-next · 1a01a075
      David S. Miller authored
      Pablo Neira Ayuso says:
      
      ====================
      Netfilter updates for net-next
      
      This is v2 including deadlock fix in conntrack ecache rework
      reported by Jakub Kicinski.
      
      The following patchset contains Netfilter updates for net-next,
      mostly updates to conntrack from Florian Westphal.
      
      1) Add a dedicated list for conntrack event redelivery.
      
      2) Include event redelivery list in conntrack dumps of dying type.
      
      3) Remove per-cpu dying list for event redelivery, not used anymore.
      
      4) Add netns .pre_exit to cttimeout to zap timeout objects before
         synchronize_rcu() call.
      
      5) Remove nf_ct_unconfirmed_destroy.
      
      6) Add generation id for conntrack extensions for conntrack
         timeout and helpers.
      
      7) Detach timeout policy from conntrack on cttimeout module removal.
      
      8) Remove __nf_ct_unconfirmed_destroy.
      
      9) Remove unconfirmed list.
      
      10) Remove unconditional local_bh_disable in init_conntrack().
      
      11) Consolidate conntrack iterator nf_ct_iterate_cleanup().
      
      12) Detect if ctnetlink listeners exist to short-circuit event
          path early.
      
      13) Un-inline nf_ct_ecache_ext_add().
      
      14) Add nf_conntrack_events autodetect ctnetlink listener mode
          and make it default.
      
      15) Add nf_ct_ecache_exist() to check for event cache extension.
      
      16) Extend flowtable reverse route lookup to include source, iif,
          tos and mark, from Sven Auhagen.
      
      17) Do not verify zero checksum UDP packets in nf_reject,
          from Kevin Mitchell.
      
      ====================
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      1a01a075
  2. 14 May, 2022 3 commits
  3. 13 May, 2022 30 commits