- 07 Apr, 2021 30 commits
-
-
Dmitry Baryshkov authored
All MSM DSI PHYs provide two clocks: byte and pixel ones. Register/unregister provided clocks from the generic place, removing boilerplate code from all MSM DSI PHY drivers. Signed-off-by:
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by:
Abhinav Kumar <abhinavk@codeaurora.org> Tested-by: Stephen Boyd <swboyd@chromium.org> # on sc7180 lazor Link: https://lore.kernel.org/r/20210331105735.3690009-11-dmitry.baryshkov@linaro.orgSigned-off-by:
Rob Clark <robdclark@chromium.org>
-
Dmitry Baryshkov authored
msm_dsi_pll_set_usecase() function is not used outside of individual DSI PHY drivers, so drop it in favour of calling the the respective set_usecase functions directly. Signed-off-by:
-
Dmitry Baryshkov authored
Signed-off-by:
-
Dmitry Baryshkov authored
With the current upstream driver the msm_dsi_phy_type enum does not make much sense: all DSI PHYs are probed using the dt bindings, the phy type is not passed between drivers. Use quirks in phy individual PHY drivers to differentiate minor harware differences and drop the enum. Signed-off-by:
-
Dmitry Baryshkov authored
Move all PLL-related callbacks into struct msm_dsi_phy_cfg. This limits the amount of data in the struct msm_dsi_pll. Signed-off-by:
-
Dmitry Baryshkov authored
The only PLL using multiple enable sequences is the 28nm PLL, which just does the single step in the loop. Push that support back into the PLL code. Signed-off-by:
-
Dmitry Baryshkov authored
Each phy version is tightly coupled with the corresponding PLL code, there is no need to keep them separate. Fuse source files together in order to simplify DSI code. Signed-off-by:
-
Dmitry Baryshkov authored
DSI PHY init callback would either map dsi_phy_regulator or dsi_phy_lane depending on the PHY type. Replace those callbacks with configuration options governing mapping those regions. Signed-off-by:
-
Dmitry Baryshkov authored
Add devm_clk_hw_register_divider() - devres version of clk_hw_register_divider(). Signed-off-by:
Stephen Boyd <sboyd@kernel.org> Link: https://lore.kernel.org/r/20210331105735.3690009-3-dmitry.baryshkov@linaro.orgSigned-off-by:
-
Dmitry Baryshkov authored
Add devm_clk_hw_register_mux() - devres-managed version of clk_hw_register_mux(). Signed-off-by:
-
Abhinav Kumar authored
Currently the error checking logic in the dp_debug module could pass zero to PTR_ERR and it causes the below kbot warnings: drivers/gpu/drm/msm/dp/dp_debug.c:378 dp_debug_init() warn: passing zero to 'PTR_ERR' drivers/gpu/drm/msm/dp/dp_debug.c:387 dp_debug_init() warn: passing zero to 'PTR_ERR' drivers/gpu/drm/msm/dp/dp_debug.c:396 dp_debug_init() warn: passing zero to 'PTR_ERR' drivers/gpu/drm/msm/dp/dp_debug.c:405 dp_debug_init() warn: passing zero to 'PTR_ERR' Debugfs functions are not supposed to be checked in the normal case so delete this code. Also it silences the above Smatch warnings that we're checking for NULL when these functions only return error pointers. Reported-by:
kernel test robot <lkp@intel.com> Reported-by:
Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by:
Stephen Boyd <swboyd@chromium.org> Link: https://lore.kernel.org/r/1614971839-2686-3-git-send-email-abhinavk@codeaurora.orgSigned-off-by:
-
Abhinav Kumar authored
Fix an incorrect NULL check reported by kbot in the MSM DP driver smatch warnings: drivers/gpu/drm/msm/dp/dp_hpd.c:37 dp_hpd_connect() error: we previously assumed 'hpd_priv->dp_cb' could be null (see line 37) Reported-by:
-
Abhinav Kumar authored
Fix a couple of indentation warnings reported by kbot across MSM DP driver: New smatch warnings: drivers/gpu/drm/msm/dp/dp_debug.c:229 dp_test_data_show() warn: inconsistent indenting drivers/gpu/drm/msm/dp/dp_power.c:203 dp_power_clk_enable() warn: inconsistent indenting Reported-by:
-
AngeloGioacchino Del Regno authored
The MSM8996 core_mmss clock was commented out due to some strange issues that others were experiencing. At least SONY Tone family is working perfectly fine with this clock declared and gets it up and running without any error. Signed-off-by:
AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> Signed-off-by:
Konrad Dybcio <konrad.dybcio@somainline.org> Link: https://lore.kernel.org/r/20210228124328.136397-1-konrad.dybcio@somainline.orgSigned-off-by:
-
Bhaskar Chowdhury authored
s/confguration/configuration/ s/Regsiters/Registers/ Signed-off-by:
Bhaskar Chowdhury <unixbhaskar@gmail.com> Link: https://lore.kernel.org/r/20210205084758.354509-1-unixbhaskar@gmail.comSigned-off-by:
-
Bernard Zhao authored
Line 1826 pr_err is redundant because memory alloc already prints an error when failed. Signed-off-by:
Bernard Zhao <bernard@vivo.com> Link: https://lore.kernel.org/r/20210202120552.14744-1-bernard@vivo.comSigned-off-by:
-
Kalyan Thota authored
Set the flag vblank_disable_immediate = true to turn off vblank irqs immediately as soon as drm_vblank_put is requested so that there are no irqs triggered during idle state. This will reduce cpu wakeups and help in power saving. To enable vblank_disable_immediate flag the underlying KMS driver needs to support high precision vblank timestamping and also a reliable way of providing vblank counter which is incrementing at the leading edge of vblank. This patch also brings in changes to support vblank_disable_immediate requirement in dpu driver. Changes in v1: - Specify reason to add vblank timestamp support. (Rob). - Add changes to provide vblank counter from dpu driver. Changes in v2: - Fix warn stack reported by Rob Clark with v2 patch. Changes in v3: - Move back to HW frame counter (Rob). Changes in v4: - Frame count mismatch was causing a DRM WARN stack spew. DPU HW will increment the frame count at the end of the sync, where as vblank will be triggered at the fetch_start counter which is calculated as v_total - vfp. This is to start fetching early for panels with low vbp w.r.t hw latency lines. Add logic to detect the line count if it falls between vactive and v_total then return incremented frame count value. Signed-off-by:
Kalyan Thota <kalyan_t@codeaurora.org> Link: https://lore.kernel.org/r/1613651746-12783-1-git-send-email-kalyan_t@codeaurora.orgSigned-off-by:
-
Rob Clark authored
Performance counts, and ALWAYS_ON counters used for capturing GPU timestamps, lose their state across suspend/resume cycles. Userspace tooling for performance monitoring needs to be aware of this. For example, after a suspend userspace needs to recalibrate it's offset between CPU and GPU time. Signed-off-by:
Jordan Crouse <jordan@cosmicpenguin.net> Link: https://lore.kernel.org/r/20210325012358.1759770-3-robdclark@gmail.comSigned-off-by:
-
Akhil P Oommen authored
The speedbin support requires nvmem driver api. So lets explicitly enable CONFIG_NVMEM to have this support. Signed-off-by:
Akhil P Oommen <akhilpo@codeaurora.org> Link: https://lore.kernel.org/r/1617630433-36506-2-git-send-email-akhilpo@codeaurora.orgSigned-off-by:
-
Akhil P Oommen authored
We were not programing the correct bit while clearing the perfcounter oob. So, clear it correctly using the new 'clear' bit. This fixes the below error: [drm:a6xx_gmu_set_oob] *ERROR* Timeout waiting for GMU OOB set PERFCOUNTER: 0x80000000 Signed-off-by:
-
Jonathan Marek authored
The driver already has support for sm8150/sm8250, but the compatibles were never added. Also inverse the non-mdp4 condition in add_display_components() to avoid having to check every new compatible in the condition. Signed-off-by:
Jonathan Marek <jonathan@marek.ca> Signed-off-by:
Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20210329120051.3401567-4-dmitry.baryshkov@linaro.orgSigned-off-by:
-
Bjorn Andersson authored
After spending a non-negligible time trying to figure out why dpu_kms_init() would dereference a NULL dpu_kms->pdev, it turns out that in addition to adding the new compatible to the msm_drv of_match_table one also need to teach add_display_components() to register the child nodes - which includes the DPU platform_device. Replace the open coded test for compatibles with a check against the match data of the mdss device to save others this trouble in the future. Signed-off-by:
-
Rob Clark authored
The previous patch fixes the user visible spelling. This one fixes the code. Oops. Signed-off-by:
-
Colin Ian King authored
There is a spelling mistake in debugfs gem stats. Fix it. Also re-align output to cater for the extra 1 character. Signed-off-by:
Colin Ian King <colin.king@canonical.com> Link: https://lore.kernel.org/r/20210406133939.425987-1-colin.king@canonical.comSigned-off-by:
-
Rob Clark authored
lock_stat + mmm_donut[1] say that this reduces contention on mm_lock significantly (~350x lower waittime-max, and ~100x lower waittime-avg) [1] https://chromium.googlesource.com/chromiumos/platform/microbenchmarks/+/refs/heads/main/mmm_donut.pySigned-off-by:
Douglas Anderson <dianders@chromium.org> Link: https://lore.kernel.org/r/20210402211226.875726-1-robdclark@gmail.comSigned-off-by:
-
Rob Clark authored
The last patch lost the breakdown of active vs inactive GEM objects in $debugfs/gem. But we can add some better stats to summarize not just active vs inactive, but also purgable/purged to make up for that. Signed-off-by:
-
Rob Clark authored
In normal cases the gem obj lock is acquired first before mm_lock. The exception is iterating the various object lists. In the shrinker path, deadlock is avoided by using msm_gem_trylock() and skipping over objects that cannot be locked. But for debugfs the straightforward thing is to split things out into a separate list of all objects protected by it's own lock. Fixes: d984457b ("drm/msm: Add priv->mm_lock to protect active/inactive lists") Signed-off-by:
-
Rob Clark authored
When the system is under heavy memory pressure, we can end up with lots of concurrent calls into the shrinker. Keeping a running tab on what we can shrink avoids grabbing a lock in shrinker->count(), and avoids shrinker->scan() getting called when not profitable. Also, we can keep purged objects in their own list to avoid re-traversing them to help cut down time in the critical section further. Signed-off-by:
-
Rob Clark authored
Unused since commit c951a9b2 ("drm/msm: Remove msm_gem_free_work") Signed-off-by:
-
Rob Clark authored
Pull in fixes from previous cycle
-
- 02 Apr, 2021 3 commits
-
-
Kalyan Thota authored
Update the 3d merge as active in the data path only if the hw block is selected in the configuration. Reported-by:
-
Dmitry Baryshkov authored
I suppose the microcode version check for a650 is incorrect. It checks for the version 1.95, while the firmware released have major version of 0: 0.91 (vulnerable), 0.99 (fixing the issue). Lower version requirements to accept firmware 0.99. Fixes: 8490f02a ("drm/msm: a6xx: Make sure the SQE microcode is safe") Cc: Akhil P Oommen <akhilpo@codeaurora.org> Cc: Jordan Crouse <jcrouse@codeaurora.org> Signed-off-by:
-
Rob Clark authored
They were reading a counter that was configured to ALWAYS_COUNT (ie. cycles that the GPU is doing something) rather than ALWAYS_ON. This isn't the thing that userspace is looking for. Signed-off-by:
-
- 01 Apr, 2021 2 commits
-
-
John Stultz authored
Commit 7bf168c8 ("drm/msm: Fix speed-bin support not to access outside valid memory"), reworked the nvmem reading of "speed_bin", but in doing so dropped handling of the -ENOENT case which was previously documented as "fine". That change resulted in the db845c board display to fail to start, with the following error: adreno 5000000.gpu: [drm:a6xx_gpu_init] *ERROR* failed to read speed-bin (-2). Some OPPs may not be supported by hardware Thus, this patch simply re-adds the ENOENT handling so the lack of the speed_bin entry isn't fatal for display, and gets things working on db845c. Cc: Rob Clark <robdclark@gmail.com> Cc: Sean Paul <sean@poorly.run> Cc: Jordan Crouse <jcrouse@codeaurora.org> Cc: Eric Anholt <eric@anholt.net> Cc: Douglas Anderson <dianders@chromium.org> Cc: linux-arm-msm@vger.kernel.org Cc: freedreno@lists.freedesktop.org Cc: Bjorn Andersson <bjorn.andersson@linaro.org> Cc: YongQin Liu <yongqin.liu@linaro.org> Reported-by:
YongQin Liu <yongqin.liu@linaro.org> Fixes: 7bf168c8 ("drm/msm: Fix speed-bin support not to access outside valid memory") Signed-off-by:
John Stultz <john.stultz@linaro.org> Reviewed-by:
-
Stephen Boyd authored
We should set the platform device's driver data to NULL here so that code doesn't assume the struct drm_device pointer is valid when it could have been destroyed. The lifetime of this pointer is managed by a kref but when msm_drm_init() fails we call drm_dev_put() on the pointer which will free the pointer's memory. This driver uses the component model, so there's sort of two "probes" in this file, one for the platform device i.e. msm_pdev_probe() and one for the component i.e. msm_drm_bind(). The msm_drm_bind() code is using the platform device's driver data to store struct drm_device so the two functions are intertwined. This relationship becomes a problem for msm_pdev_shutdown() when it tests the NULL-ness of the pointer to see if it should call drm_atomic_helper_shutdown(). The NULL test is a proxy check for if the pointer has been freed by kref_put(). If the drm_device has been destroyed, then we shouldn't call the shutdown helper, and we know that is the case if msm_drm_init() failed, therefore set the driver data to NULL so that this pointer liveness is tracked properly. Fixes: 9d5cbf5f ("drm/msm: add shutdown support for display platform_driver") Cc: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Cc: Fabio Estevam <festevam@gmail.com> Cc: Krishna Manikandan <mkrishn@codeaurora.org> Signed-off-by:
-
- 23 Mar, 2021 1 commit
-
-
Kalyan Thota authored
DPU runtime resume will request for a min vote on the AXI bus as it is a necessary step before turning ON the AXI clock. The change does below 1) Move the icc path set before requesting runtime get_sync. 2) remove the dependency of hw catalog for min ib vote as it is initialized at a later point. Signed-off-by:
Matthias Kaehlcke <mka@chromium.org> Signed-off-by:
-
- 21 Mar, 2021 2 commits
-
-
Fabio Estevam authored
When putting iMX5 into suspend, the following flow is observed: [ 70.023427] [<c07755f0>] (msm_atomic_commit_tail) from [<c06e7218>] (commit_tail+0x9c/0x18c) [ 70.031890] [<c06e7218>] (commit_tail) from [<c0e2920c>] (drm_atomic_helper_commit+0x1a0/0x1d4) [ 70.040627] [<c0e2920c>] (drm_atomic_helper_commit) from [<c06e74d4>] (drm_atomic_helper_disable_all+0x1c4/0x1d4) [ 70.050913] [<c06e74d4>] (drm_atomic_helper_disable_all) from [<c0e2943c>] (drm_atomic_helper_suspend+0xb8/0x170) [ 70.061198] [<c0e2943c>] (drm_atomic_helper_suspend) from [<c06e84bc>] (drm_mode_config_helper_suspend+0x24/0x58) In the i.MX5 case, priv->kms is not populated (as i.MX5 does not use any of the Qualcomm display controllers), causing a NULL pointer dereference in msm_atomic_commit_tail(): [ 24.268964] 8<--- cut here --- [ 24.274602] Unable to handle kernel NULL pointer dereference at virtual address 00000000 [ 24.283434] pgd = (ptrval) [ 24.286387] [00000000] *pgd=ca212831 [ 24.290788] Internal error: Oops: 17 [#1] SMP ARM [ 24.295609] Modules linked in: [ 24.298777] CPU: 0 PID: 197 Comm: init Not tainted 5.11.0-rc2-next-20210111 #333 [ 24.306276] Hardware name: Freescale i.MX53 (Device Tree Support) [ 24.312442] PC is at msm_atomic_commit_tail+0x54/0xb9c [ 24.317743] LR is at commit_tail+0xa4/0x1b0 Fix the problem by calling drm_mode_config_helper_suspend/resume() only when priv->kms is available. Fixes: ca8199f1 ("drm/msm/dpu: ensure device suspend happens during PM sleep") Signed-off-by:
Fabio Estevam <festevam@gmail.com> Signed-off-by:
-
Dmitry Baryshkov authored
If GPU components have failed to bind, shutdown callback would fail with the following backtrace. Add safeguard check to stop that oops from happening and allow the board to reboot. [ 66.617046] Unable to handle kernel NULL pointer dereference at virtual address 0000000000000000 [ 66.626066] Mem abort info: [ 66.628939] ESR = 0x96000006 [ 66.632088] EC = 0x25: DABT (current EL), IL = 32 bits [ 66.637542] SET = 0, FnV = 0 [ 66.640688] EA = 0, S1PTW = 0 [ 66.643924] Data abort info: [ 66.646889] ISV = 0, ISS = 0x00000006 [ 66.650832] CM = 0, WnR = 0 [ 66.653890] user pgtable: 4k pages, 48-bit VAs, pgdp=0000000107f81000 [ 66.660505] [0000000000000000] pgd=0000000100bb2003, p4d=0000000100bb2003, pud=0000000100897003, pmd=0000000000000000 [ 66.671398] Internal error: Oops: 96000006 [#1] PREEMPT SMP [ 66.677115] Modules linked in: [ 66.680261] CPU: 6 PID: 352 Comm: reboot Not tainted 5.11.0-rc2-00309-g79e3faa7 #38 [ 66.688473] Hardware name: Qualcomm Technologies, Inc. Robotics RB5 (DT) [ 66.695347] pstate: 60400005 (nZCv daif +PAN -UAO -TCO BTYPE=--) [ 66.701507] pc : msm_atomic_commit_tail+0x78/0x4e0 [ 66.706437] lr : commit_tail+0xa4/0x184 [ 66.710381] sp : ffff8000108f3af0 [ 66.713791] x29: ffff8000108f3af0 x28: ffff418c44337000 [ 66.719242] x27: 0000000000000000 x26: ffff418c40a24490 [ 66.724693] x25: ffffd3a842a4f1a0 x24: 0000000000000008 [ 66.730146] x23: ffffd3a84313f030 x22: ffff418c444ce000 [ 66.735598] x21: ffff418c408a4980 x20: 0000000000000000 [ 66.741049] x19: 0000000000000000 x18: ffff800010710fbc [ 66.746500] x17: 000000000000000c x16: 0000000000000001 [ 66.751954] x15: 0000000000010008 x14: 0000000000000068 [ 66.757405] x13: 0000000000000001 x12: 0000000000000000 [ 66.762855] x11: 0000000000000001 x10: 00000000000009b0 [ 66.768306] x9 : ffffd3a843192000 x8 : ffff418c44337000 [ 66.773757] x7 : 0000000000000000 x6 : 00000000a401b34e [ 66.779210] x5 : 00ffffffffffffff x4 : 0000000000000000 [ 66.784660] x3 : 0000000000000000 x2 : ffff418c444ce000 [ 66.790111] x1 : ffffd3a841dce530 x0 : ffff418c444cf000 [ 66.795563] Call trace: [ 66.798075] msm_atomic_commit_tail+0x78/0x4e0 [ 66.802633] commit_tail+0xa4/0x184 [ 66.806217] drm_atomic_helper_commit+0x160/0x390 [ 66.811051] drm_atomic_commit+0x4c/0x60 [ 66.815082] drm_atomic_helper_disable_all+0x1f4/0x210 [ 66.820355] drm_atomic_helper_shutdown+0x80/0x130 [ 66.825276] msm_pdev_shutdown+0x14/0x20 [ 66.829303] platform_shutdown+0x28/0x40 [ 66.833330] device_shutdown+0x158/0x330 [ 66.837357] kernel_restart+0x40/0xa0 [ 66.841122] __do_sys_reboot+0x228/0x250 [ 66.845148] __arm64_sys_reboot+0x28/0x34 [ 66.849264] el0_svc_common.constprop.0+0x74/0x190 [ 66.854187] do_el0_svc+0x24/0x90 [ 66.857595] el0_svc+0x14/0x20 [ 66.860739] el0_sync_handler+0x1a4/0x1b0 [ 66.864858] el0_sync+0x174/0x180 [ 66.868269] Code: 1ac020a0 2a000273 eb02007f 54ffff01 (f9400285) [ 66.874525] ---[ end trace 20dedb2a3229fec8 ]--- Fixes: 9d5cbf5f ("drm/msm: add shutdown support for display platform_driver") Signed-off-by:
-
- 17 Mar, 2021 2 commits
-
-
Rob Clark authored
We have seen a couple cases where low memory situations cause something bad to happen, followed by a flood of these messages obscuring the root cause. Lets ratelimit the dmesg spam so that next time it happens we don't lose the kernel traces leading up to this. Signed-off-by:
-
Konrad Dybcio authored
While passing the A530-specific lm_setup func to A530 and A540 to !A530 was fine back when only these two were supported, it certainly is not a good idea to send A540 specifics to smaller GPUs like A508 and friends. Signed-off-by:
-
