- 14 Jun, 2024 40 commits
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Ivan Lipski authored
[WHY] Coverity analysis flagged this ternary operation as DEADCODE. Since 'total_y_free_entry' is initialized as 0x200 and 'total_c_free_entry' is initialized as 0x140, and they never change values before the ternary operator, so 'total_y_free_entry' is always greater 'total_c_free_entry', 'so small_free_entry' is always set to 'total_c_free_entry'. [HOW] Replace the ternary operator with the variable declaration. Signed-off-by:
Ivan Lipski <ivlipski@amd.com> Acked-by:
Zaeem Mohamed <zaeem.mohamed@amd.com> Tested-by:
Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Ivan Lipski authored
[WHY] Coverity analysis flagged this code as DEADCODE since the condition and return in the outer loop are never reached. All operations with the 'dwb_pipe' variable happen in the inner loop, that already contains the same check with the 'MAX_DWB_PIPES'. The later check condition cannot occur before the check condition in the inner loop, thus the later condition is unreacable. [HOW] Remove the unreachable condition. Acked-by:
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Ivan Lipski authored
[WHY] Coverity analysis flagged the two if conditions in dcn30_dpp.c and dcn401_dpp.c as DEADCODE since they are never true, since the variable 'program_prealpha_dealpha' is initialized at 0 and never chagnes. [HOW] Removed the variable 'program_prealpha_dealpha' and the if conditions. Acked-by:
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Wenjing Liu authored
[why] OPP input rect aka odm slice rect is a hardware dependent parameter that can't be determined by SPL software logic. Therefore we need to explicitly pass odm slice rect in. So ODM slice rect calculation is moved out of SPL. [how] add odm_slice_rect parameter in spl_in Reviewed-by:
Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by:
Wenjing Liu <wenjing.liu@amd.com> Tested-by:
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Wenjing Liu authored
[why] When optc uses two pixel per container, each ODM slice width must be an even number. [how] If ODM slice width is odd number increase it by 1. Reviewed-by:
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Dennis Chan authored
When PHY power off, the DP_SEC_CNTL cannot be configured and cause disable Adaptive sync SDP failed. Regarding the issue, the driver will disabled AS-SDP in replay state machine. Reviewed-by:
Dennis Chan <dennis.chan@amd.com> Tested-by:
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ChunTao Tso authored
[Why] Because ABM will wait VStart to start getting histogram data, it will cause we can't enter IPS while full screnn video playing. [How] Modify the panel refresh rate to the maximun multiple of current refresh rate Reviewed-by:
ChunTao Tso <ChunTao.Tso@amd.com> Tested-by:
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Leon Huang authored
[Why] Dmub provides several Replay residency calculation methods, but current interface only supports either ALPM or PHY mode [How] Modify the interface for supporting different types of Replay residency calculation. Reviewed-by:
Leon Huang <Leon.Huang1@amd.com> Tested-by:
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ChunTao Tso authored
[Why] The original coasting vtotal is 2 bytes, and it need to be amended to 4 bytes because low hz case. [How] Amend coasting vtotal from 2 bytes to 4 bytes. Reviewed-by:
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pochchan authored
For some specific panel, it need to use TPS3 rather than use TP2 in ALPM when DSC is enabled. Reviewed-by:
pochchan <pochchan@amd.com> Tested-by:
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Nicholas Kazlauskas authored
[Why] We can hang in place trying to send commands when the DMCUB isn't powered on. [How] For functions that execute within a DC context or DC lock we can wrap the direct calls to dm_execute_dmub_cmd/list with code that exits idle power optimizations and reallows once we're done with the command submission on success. For DM direct submissions the DM will need to manage the enter/exit sequencing manually. We cannot invoke a DMCUB command directly within the DM execution helper or we can deadlock. Reviewed-by:
Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Tested-by:
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Nicholas Kazlauskas authored
[Why] These functions can be called from high IRQ levels and the OS will hang if it tries to use a usleep_highres or a msleep. [How] Replace the flseep with a udelay for dmub_replay_enable. Reviewed-by:
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Christian König authored
This reverts commit b8c415e3 ("drm/amdgpu: take runtime pm reference when we attach a buffer") and commit 425285d3 ("drm/amdgpu: add amdgpu runpm usage trace for separate funcs"). Taking a runtime pm reference for DMA-buf is actually completely unnecessary and even dangerous. The problem is that calling pm_runtime_get_sync() from the DMA-buf callbacks is illegal because we have the reservation locked here which is also taken during resume. So this would deadlock. When the buffer is in GTT it is still accessible even when the GPU is powered down and when it is in VRAM the buffer gets migrated to GTT before powering down. The only use case which would make it mandatory to keep the runtime pm reference would be if we pin the buffer into VRAM, and that's not something we currently do. v2: improve the commit message Signed-off-by:
Christian König <christian.koenig@amd.com> Reviewed-by:
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Rodrigo Siqueira authored
Use dc_wake_and_execute_gpint with DM_DMUB_WAIT_TYPE_WAIT_WITH_REPLY to get the replay state. Signed-off-by:
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Yang Wang authored
refine imu firmware loading Signed-off-by:
Yang Wang <kevinyang.wang@amd.com> Reviewed-by:
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Yang Wang authored
refine pmfw/smu firmware loading Signed-off-by:
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Yang Wang authored
refine gmc firmware loading Signed-off-by:
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Yang Wang authored
refine vpe firmware loading Signed-off-by:
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Yang Wang authored
refine vcn firmware loading Signed-off-by:
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Yang Wang authored
adjust the function position to better match aca/mca fini code in ras_fini(). Signed-off-by:
Tao Zhou <tao.zhou1@amd.com> Signed-off-by:
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Bob Zhou authored
To fix potential overflowed constant warning, modify the variables to u32 for getting the return value of RREG32_SOC15(). Signed-off-by:
Bob Zhou <bob.zhou@amd.com> Acked-by:
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Harish Kasiviswanathan authored
To achieve full occupancy CP hardware needs to know if CUs in SE are symmetrically or asymmetrically harvested v2: Reset is_symmetric_cus for each loop Signed-off-by:
Harish Kasiviswanathan <Harish.Kasiviswanathan@amd.com> Acked-by:
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Lijo Lazar authored
Skip scheduling coredump when gpu reset is intentionally triggered through debugfs. Signed-off-by:
Lijo Lazar <lijo.lazar@amd.com> Reviewed-by:
Asad Kamal <asad.kamal@amd.com> Reviewed-by:
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Yang Wang authored
refine sdma firmware loading Signed-off-by:
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Yang Wang authored
refine psp firmware loading Signed-off-by:
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Yunxiang Li authored
We need to take the reset domain lock before talking to MES. While in this case we can take the lock inside the mes helper. We can't do so for most other mes helpers since they are used during reset. So for consistency sake we add the lock here. Signed-off-by:
Yunxiang Li <Yunxiang.Li@amd.com> Reviewed-by:
Felix Kuehling <felix.kuehling@amd.com> Signed-off-by:
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Yang Wang authored
v1: refine mes firmware loading v2: use dev_info instead of DRM_INFO Signed-off-by:
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Mukul Joshi authored
Add missing locking at a few places when calling MES APIs to ensure exclusive access to MES queue. Signed-off-by:
Mukul Joshi <mukul.joshi@amd.com> Reviewed-by:
Kent Russell <kent.russell@amd.com> Signed-off-by:
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Mario Limonciello authored
Currently, amdgpu will always set up the brightness at 100% when it loads. However this is jarring when the BIOS has it previously programmed to a much lower value. The ACPI ATIF method includes two members for "ac_level" and "dc_level". These represent the default values that should be used if the system is brought up in AC and DC respectively. Use these values to set up the default brightness when the backlight device is registered. v2: squash in ACPI fix Reviewed-by:
Leo Li <sunpeng.li@amd.com> Acked-by:
Mario Limonciello <mario.limonciello@amd.com> Signed-off-by:
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David (Ming Qiang) Wu authored
Similar to commit 813e7d4c where some kernel log messages are dropped. With this commit, more log messages in older version of VCN/JPEG code are dropped. Acked-by:
Leo Liu <leo.liu@amd.com> Signed-off-by:
David (Ming Qiang) Wu <David.Wu3@amd.com> Signed-off-by:
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Ivan Lipski authored
Revert "drm/amd/display: Add NULL check for 'afb' before dereferencing in amdgpu_dm_plane_handle_cursor_update" [WHY] This patch is a dupplicate implementation of 14bcf29b, which we are reverting due to a regression with kms_plane_cursor IGT tests. This reverts commit 38e6f715. Reviewed-by:
Srinivasan Shanmugam <srinivasan.shanmugam@amd.com> Tested-by:
George Zhang <George.zhang@amd.com> Signed-off-by:
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Ivan Lipski authored
[WHY] This commit introduced a regression with kms_plane_cursor IGT tests, causing AMD Asics to fail these tests. This reverts commit ce66ffd9. Reviewed-by:
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Yang Wang authored
refine gpu_info firmware loading Signed-off-by:
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Hamza Mahfooz authored
We can't read/write to DCN registers while in IPS. Since, that can cause the system to hang. So, before proceeding with the access in that scenario, force the system out of IPS. Cc: stable@vger.kernel.org # 6.6+ Reviewed-by:
Roman Li <roman.li@amd.com> Signed-off-by:
Hamza Mahfooz <hamza.mahfooz@amd.com> Signed-off-by:
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Yang Wang authored
v1: Adding formatting string feature to improve function flexibility. v2: modify macro name to ADMGPU_UCODE_MAX_NAME. Signed-off-by:
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Bob Zhou authored
To fix potential overflowed constant warning reported by Coverity, modify the variables to uint32_t. Signed-off-by:
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Yunxiang Li authored
We need to take the reset domain lock before flush hdp. We can't put the lock inside amdgpu_device_flush_hdp itself because it is used during reset where we already take the write side lock. Signed-off-by:
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Yunxiang Li authored
Which method is used to flush tlb does not depend on whether a reset is in progress or not. We should skip flush altogether if the GPU will get reset. So put both path under reset_domain read lock. Signed-off-by:
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Yunxiang Li authored
Here since we are in reset and takes the reset_domain write side lock already. We can't use the flush tlb helper which tries to take the read side. Signed-off-by:
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Yunxiang Li authored
When amdgpu_gart_invalidate_tlb helper is introduced this part was left out of the conversion. Avoid the code duplication here. Signed-off-by:
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