- 24 Apr, 2019 10 commits
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Jérôme Glisse authored
The debugfs take reference on fence without dropping them. Signed-off-by:
Jérôme Glisse <jglisse@redhat.com> Cc: Christian König <christian.koenig@amd.com> Cc: Daniel Vetter <daniel.vetter@ffwll.ch> Cc: Sumit Semwal <sumit.semwal@linaro.org> Cc: linux-media@vger.kernel.org Cc: dri-devel@lists.freedesktop.org Cc: linaro-mm-sig@lists.linaro.org Cc: Stéphane Marchesin <marcheu@chromium.org> Cc: stable@vger.kernel.org Reviewed-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
Sumit Semwal <sumit.semwal@linaro.org> Link: https://patchwork.freedesktop.org/patch/msgid/20181206161840.6578-1-jglisse@redhat.com
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Yannick Fertré authored
Add support of DRM_FORMAT_MOD_LINEAR modifier. Signed-off-by:
Mickael Reulier <mickael.reulier@st.com> Signed-off-by:
Yannick Fertré <yannick.fertre@st.com> Acked-by:
Philippe Cornu <philippe.cornu@st.com> Link: https://patchwork.freedesktop.org/patch/msgid/1554283514-2960-1-git-send-email-yannick.fertre@st.comSigned-off-by:
Benjamin Gaignard <benjamin.gaignard@linaro.org>
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Yannick Fertré authored
Display controller reset must be done as soon as possible after enable the clock to avoid partial refresh on screen. Signed-off-by:
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Yannick Fertré authored
If the number of layer is greater than LTDC_MAX_LAYER, we can have memory overflow when reading plane_fpsi[]. Signed-off-by:
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Yannick Fertré authored
Plane updates must be synchronized on vblank with the shadow register mechanism to avoid partial refresh on screen. Signed-off-by:
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Yannick Fertré authored
Wrong DISPLAY_FLAGS used to set the data enable polarity. Signed-off-by:
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Philippe Cornu authored
Use DRM_WARN() instead of DRM_DEBUG_DRIVER() to better inform the user in case of fifo underruns or transfer errors. Signed-off-by:
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Yannick Fertré authored
Interrupt register must be disabled before call of devm_request_threaded_irq function to avoid dummy interruption. Signed-off-by:
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Maarten Lankhorst authored
Signed-off-by:
Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Reviewed-by:
Daniel Stone <daniels@collabora.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190301125627.7285-4-maarten.lankhorst@linux.intel.com
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Maarten Lankhorst authored
We already have __drm_atomic_helper_connector_reset() and __drm_atomic_helper_plane_reset(), extend this to crtc as well. This will allow us to set default values in the crtc_state, without having to do it in each driver separately. Of all drivers that need conversion, only nouveau is done in this commit, because it wrote its own __drm_atomic_helper_crtc_reset(), clashing with the drm core. Signed-off-by:
Daniel Vetter <daniel.vetter@ffwll.ch> Link: https://patchwork.freedesktop.org/patch/msgid/20190301125627.7285-3-maarten.lankhorst@linux.intel.com
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- 23 Apr, 2019 21 commits
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Marco Felsch authored
Add support the Evervision VGG804821 800x480 5.0" WVGA TFT panel. Signed-off-by:
Marco Felsch <m.felsch@pengutronix.de> Signed-off-by:
Thierry Reding <treding@nvidia.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190416100645.21689-4-m.felsch@pengutronix.de
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Marco Felsch authored
Add device tree bindings for the Evervision VG804821 800x480 5.0" LCD TFT parallel panel. Signed-off-by:
Rob Herring <robh@kernel.org> Signed-off-by:
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Marco Felsch authored
Evervision Electronics is a panel manufacturer from Taipei. http://www.evervisionlcd.com/index.php?lang=enSigned-off-by:
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Andreas Pretzsch authored
Add support for the EDT ET035012DM6 3.5" 320x240 QVGA 24-bit RGB TFT. The datasheet with all specs can be retrieved online: https://www.glynshop.com/erp/owweb/Daten/DSS/EDT/Products/ \ Specifications/Active%20Displays/ET035012DM6.pdf Signed-off-by:
Andreas Pretzsch <apr@cn-eng.de> [m.felsch@pengutronix.de: adapt commit message] [m.felsch@pengutronix.de: rm unecessary comments] [m.felsch@pengutronix.de: correct data_enable polarity] Signed-off-by:
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Marco Felsch authored
Add support for the ET035012DM6 3.5" QVGA TFT LCD panel. The datasheet can be retrieved online: https://www.glynshop.com/erp/owweb/Daten/DSS/EDT/Products/ \ Specifications/Active%20Displays/ET035012DM6.pdf Signed-off-by:
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Souptick Joarder authored
Remove duplicate header which is included twice. Signed-off-by:
Souptick Joarder <jrdr.linux@gmail.com> Signed-off-by:
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Jyri Sarha authored
Add support for Three Five displays TFC S9700RTWV43TR-01B 800x480 panel with resistive touch found on TI's AM335X-EVM. Signed-off-by:
Jyri Sarha <jsarha@ti.com> Signed-off-by:
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Jyri Sarha authored
Add bindign for TFC S9700RTWV43TR-01B 7" Three Five Corp 800x480 LCD panel with resistive touch. The panel is found on TI AM335x-evm. Signed-off-by:
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Marek Vasut authored
The EDT ETM0430G0DH6 is 4.3" 480x272 panel, which can be supported by the simple panel driver. Signed-off-by:
Marek Vasut <marex@denx.de> Cc: Philipp Zabel <p.zabel@pengutronix.de> Cc: Thierry Reding <treding@nvidia.com> Signed-off-by:
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Marek Vasut authored
Document the Emerging Display Technology Corp. (EDT) ETM0430G0DH6 display, which is a 480x272 4.3" TFT display. Signed-off-by:
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Peter Ujfalusi authored
In case mipi_dsi_attach() fails remove the registered panel to avoid added panel without corresponding device. Signed-off-by:
Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by:
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Peter Ujfalusi authored
The panel is similar to OSD101T2045-53TS (which is handled by panel-simple) with one big difference: osd101t2587-53ts needs MIPI_DSI_TURN_ON_PERIPHERAL message to be sent from the host to be operational and thus can not be handled by panel-simple. Signed-off-by:
Sam Ravnborg <sam@ravnborg.org> Signed-off-by:
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Peter Ujfalusi authored
This adds the device-tree bindings for the OSD101T2587-53TS 10.1" 1920x1200 panel from One Stop Displays. Note: the panel is similar to OSD101T2045-53TS, but it needs additional MIPI_DSI_TURN_ON_PERIPHERAL message from the host. Signed-off-by:
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Peter Ujfalusi authored
Add support for the OSD101T2045-53TS 10.1" 1920x1200 panel from One Stop Displays to the panel-simple driver Signed-off-by:
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Peter Ujfalusi authored
This adds the device-tree bindings for the OSD101T2045-53TS 10.1" 1920x1200 panel from One Stop Displays. Signed-off-by:
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Paweł Chmiel authored
This patch adds Samsung S6E63M0 AMOLED LCD panel driver, connected over spi. It's based on already removed, non-device-tree S6E63M0 driver and panel-samsung-ld9040. It can be found for example in some of Samsung Aries based phones. Signed-off-by:
Paweł Chmiel <pawel.mikolaj.chmiel@gmail.com> Reviewed-by:
Andrzej Hajda <a.hajda@samsung.com> Signed-off-by:
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Jonathan Bakker authored
This commit adds documentation for Samsung S6E63M0 AMOLED LCD panel driver. Signed-off-by:
Jonathan Bakker <xc-racer2@live.ca> Signed-off-by:
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Fabio Estevam authored
Add support for the VXT VL050-8048NT-C01 800x480 panel to the panel-simple driver. This panel is used on some boards manufactured by TechNexion, such as imx7d-pico. Reviewed-by:
Otavio Salvador <otavio@ossystems.com.br> Reviewed-by:
Fabio Estevam <festevam@gmail.com> Signed-off-by:
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Fabio Estevam authored
The VXT VL050-8048NT-C01 is a TFT LCD panel with a 800x480 resolution connected via 24 width parallel interface. Reviewed-by:
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Fabio Estevam authored
VXT Ltd is a manufacturer of projected capacitive touch panel and display solutions: http://www.vxt.com.tw/Reviewed-by:
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Chris Wilson authored
sync_dump() is an unused, unexported, function that adds 64k to the kernel image and doesn't even provide locking around the global array it uses. add/remove: 0/2 grow/shrink: 0/0 up/down: 0/-65734 (-65734) Function old new delta sync_dump 198 - -198 sync_dump_buf 65536 - -65536 Signed-off-by:
Chris Wilson <chris@chris-wilson.co.uk> Cc: Sumit Semwal <sumit.semwal@linaro.org> Cc: Gustavo Padovan <gustavo@padovan.org> Reviewed-by:
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- 22 Apr, 2019 1 commit
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Thierry Reding authored
Sam has been helping out a lot with reviewing DRM panel patches. Add him as reviewer to help him do this important work. Signed-off-by:
Jagan Teki <jagan@amarulasolutions.com> Signed-off-by:
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- 20 Apr, 2019 1 commit
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Peter Griffin authored
On Hikey board all lima ip blocks are shared with one irq. This patch avoids a NULL ptr deref crash on this platform on startup. Tested with Weston and kmscube. Signed-off-by:
Peter Griffin <peter.griffin@linaro.org> Cc: Rob Herring <robh@kernel.org> Cc: Daniel Vetter <daniel@ffwll.ch> Cc: Qiang Yu <yuq825@gmail.com> Signed-off-by:
Qiang Yu <yuq825@gmail.com> Link: https://patchwork.freedesktop.org/patch/msgid/1555662781-22570-7-git-send-email-peter.griffin@linaro.org
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- 19 Apr, 2019 1 commit
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Philip Yang authored
After patch "drm: Use the same mmap-range offset and size for GEM and TTM", application failed to create bo of system memory because drm mmap_range size decrease to 64GB from original 1TB. This is not big enough for applications. Increase the drm mmap_range size to 1TB. Reviewed-by:
Thomas Zimmermann <tzimmermann@suse.de> Reviewed-by:
Philip Yang <Philip.Yang@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190417221507.933-1-Philip.Yang@amd.com
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- 18 Apr, 2019 6 commits
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Eric Anholt authored
It is the expectation of existing userspace (X11 + Mesa, in particular) that jobs submitted to the kernel against a shared BO will get implicitly synchronized by their submission order. If we want to allow clever userspace to disable implicit synchronization, we should do that under its own submit flag (as amdgpu and lima do). Note that we currently only implicitly sync for the rendering pass, not binning -- if you texture-from-pixmap in the binning vertex shader (vertex coordinate generation), you'll miss out on synchronization. Fixes flickering when multiple clients are running in parallel, particularly GL apps and compositors. v2: Fix a missing refcount on the CSD done fence for L2 cleaning. Signed-off-by:
Eric Anholt <eric@anholt.net> Link: https://patchwork.freedesktop.org/patch/msgid/20190416225856.20264-6-eric@anholt.netAcked-by:
Rob Clark <robdclark@gmail.com>
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Eric Anholt authored
We only set the excl (possible-writing) fence pointer and never add a shared (read-only) fence. Signed-off-by:
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Eric Anholt authored
The compute shader dispatch interface is pretty simple -- just pass in the regs that userspace has passed us, with no CLs to run. However, with no CL to run it means that we need to do manual cache flushing of the L2 after the HW execution completes (for SSBO, atomic, and image_load_store writes that are the output of compute shaders). This doesn't yet expose the L2 cache's ability to have a region of the address space not write back to memory (which could be used for shared_var storage). So far, the Mesa side has been tested on V3D v4.2 simpenrose (passing the ES31 tests), and on the kernel side on 7278 (failing atomic compswap tests in a way that doesn't reproduce on simpenrose). v2: Fix excessive allocation for the clean_job (reported by Dan Carpenter). Keep refs on jobs until clean_job is finished, to avoid spurious MMU errors if the output BOs are freed by userspace before L2 cleaning is finished. Signed-off-by: -
Eric Anholt authored
The CL submission had two jobs embedded in an exec struct. When I added TFU support, I had to replicate some of the exec stuff and some of the job stuff. As I went to add CSD, it became clear that actually what was in exec should just be in the two CL jobs, and it would let us share a lot more code between the 4 queues. v2: Fix missing error path in TFU ioctl's bo[] allocation. Signed-off-by:
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Eric Anholt authored
All consumers wanted drm_gem_object * now. Signed-off-by:
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Paul Kocialkowski authored
Our driver makes a typical use of CMA, with GEM object allocated as GEM CMA objects. Use DRM_GEM_CMA_VMAP_DRIVER_OPS to describe the ops instead of duplicating them. Because DRM_GEM_CMA_VMAP_DRIVER_OPS implements a gem_create_object op which sets per-object funcs (drm_cma_gem_default_funcs), we can also get rid of free_object_unlocked and gem_vm_ops, which are superseded by the object funcs. Signed-off-by:
Paul Kocialkowski <paul.kocialkowski@bootlin.com> Signed-off-by:
Maxime Ripard <maxime.ripard@bootlin.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190418130509.3569-1-paul.kocialkowski@bootlin.com
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