- 20 Sep, 2023 14 commits
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David Francis authored
These flags (for GEM and SVM allocations) allocate memory that allows for system-scope atomic semantics. On GFX943 these flags cause caches to be avoided on non-local memory. On all other ASICs they are identical in functionality to the equivalent COHERENT flags. Corresponding Thunk patch is at https://github.com/RadeonOpenCompute/ROCT-Thunk-Interface/pull/88Reviewed-by:
David Yat Sin <David.YatSin@amd.com> Signed-off-by:
David Francis <David.Francis@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Jonathan Kim authored
There are cases where HSA runtime is not enabled through the AMDKFD_IOC_RUNTIME_ENABLE call when adding queues and the MES ADD_QUEUE API should clear the MES process context instead of SET_SHADER_DEBUGGER. Such examples are legacy HSA runtime builds that do not support the current exception handling and running KFD tests. The only time ADD_QUEUE.skip_process_ctx_clear is required is for debugger use cases where a debugged process is always runtime enabled when adding a queue. Tested-by:
Shikai Guo <shikai.guo@amd.com> Signed-off-by:
Jonathan Kim <jonathan.kim@amd.com> Acked-by:
Felix Kuehling <felix.kuehling@amd.com> Reviewed-by:
Eric Huang <jinhuieric.huang@amd.com> Signed-off-by:
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Yang Wang authored
add amdgpu mca debug sysfs support. Signed-off-by:
Yang Wang <kevinyang.wang@amd.com> Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
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Alex Deucher authored
Add missing IP discovery info. Reviewed-by:
Christian König <christian.koenig@amd.com> Reviewed-by:
Lang Yu <lang.yu@amd.com> Signed-off-by:
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Yang Wang authored
add amdgpu smu mca dump feature support. Signed-off-by:
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Lijo Lazar authored
pp_dpm_*clk nodes also could show the frequencies when a clock is in 'sleep' state. Add documentation related to that. Signed-off-by:
Lijo Lazar <lijo.lazar@amd.com> Acked-by:
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Mario Limonciello authored
Seamless boot can technically be supported as far back as DCN1 but to avoid regressions on older hardware, enable it for DCN3 and later. If users report using the module parameter that it works on older ASICs as well, this can be adjusted. Reviewed-by:
Harry Wentland <harry.wentland@amd.com> Signed-off-by:
Mario Limonciello <mario.limonciello@amd.com> Signed-off-by:
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Mario Limonciello authored
The module parameter can be used to test more easily enabling seamless boot support on additional ASICs. Reviewed-by:
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Timmy Tsai authored
During jpeg init, CPU writes to frame buffer which can be cached by HDP, occasionally causing invalid header to be sent to MMSCH. Perform HDP flush after writing to frame buffer before continuing with jpeg init sequence. Reviewed-by:
Timmy Tsai <timmtsai@amd.com> Signed-off-by:
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Mario Limonciello authored
This will allow base driver to dictate whether seamless should be enabled. No intended functional changes. Reviewed-by:
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Mario Limonciello authored
`amdgpu_gmc_get_vbios_allocations` has a special case for how to bring up yellow carp when amdgpu discovery is turned off. As this ASIC ships with discovery turned on, it's generally dead code and worse it causes `adev->mman.keep_stolen_vga_memory` to not be initialized for yellow carp. Remove it. Signed-off-by:
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Lijo Lazar authored
For SMU v13.0.6, keep GFX deep sleep clock reporting style consistent with that of other clocks. Sample format below. S: 78Mhz * 0: 600Mhz 1: 800Mhz Signed-off-by:
Evan Quan <evan.quan@amd.com> Signed-off-by:
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Lijo Lazar authored
On SMU v13.0.6, effective clocks are reported by FW which won't exactly match with DPM level. Report the current clock based on the values matching closest to the effective clock. Also, when deep sleep is applied to a clock, report it with a special level "S:" as in sample clock levels below S: 19Mhz * 0: 615Mhz 1: 800Mhz 2: 888Mhz 3: 1000Mhz Signed-off-by:
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Lijo Lazar authored
Use an inline function for version check. Gives more flexibility to handle any format changes. Signed-off-by:
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- 12 Sep, 2023 3 commits
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Alex Deucher authored
Implement support for remapping the HDP aperture registers for NBIO 7.11. Reviewed-by:
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Alex Deucher authored
Implement support for setting up the VCN doorbell range for NBIO 7.11. Reviewed-by:
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Harish Kasiviswanathan authored
Heavy-weight TLB flush is required after unmap on all GPUs for correctness and security. Signed-off-by:
Harish Kasiviswanathan <Harish.Kasiviswanathan@amd.com> Reviewed-by:
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- 11 Sep, 2023 23 commits
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David Francis authored
On some APU systems, there is no atom context and so the atom_context struct is null. Add a check to the VBIOS_INFO branch of amdgpu_info_ioctl to handle this case, returning all zeroes. Reviewed-by:
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André Almeida authored
Create a module option to disable soft recoveries on amdgpu, making every recovery go through the device reset path. This option makes easier to force device resets for testing and debugging purposes. Signed-off-by:
André Almeida <andrealmeid@igalia.com> Reviewed-by:
Hamza Mahfooz <hamza.mahfooz@amd.com> Signed-off-by:
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André Almeida authored
Merge all developer debug options available as separated module parameters in one, making it obvious that are for developers. Drop the obsolete module options in favor of the new ones. Signed-off-by:
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Randy Dunlap authored
Fix the typo in the kernel-doc for @replay_mode to prevent kernel-doc warnings: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h:623: warning: Incorrect use of kernel-doc format: * @replay mode: Replay supported drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h:626: warning: Function parameter or member 'replay_mode' not described in 'amdgpu_hdmi_vsdb_info' Fixes: ec8e59cb ("drm/amd/display: Get replay info from VSDB") Signed-off-by:
Randy Dunlap <rdunlap@infradead.org> Reported-by:
kernel test robot <lkp@intel.com> Cc: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Cc: Harry Wentland <harry.wentland@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: Leo Li <sunpeng.li@amd.com> Cc: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Cc: amd-gfx@lists.freedesktop.org Cc: dri-devel@lists.freedesktop.org Signed-off-by:
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Jiapeng Chong authored
No functional modification involved. drivers/gpu/drm/amd/amdgpu/../display/dc/link/link_dpms.c:2476 link_set_dpms_on() warn: if statement not indented. Reported-by:
Abaci Robot <abaci@linux.alibaba.com> Closes: https://bugzilla.openanolis.cn/show_bug.cgi?id=6502Signed-off-by:
Jiapeng Chong <jiapeng.chong@linux.alibaba.com> Signed-off-by:
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Ian Chen authored
Add flag skip_implict_edp_power_control check in function dcn32_disable_link_output to fix DCN35 issue. Reviewed-by:
Robin Chen <robin.chen@amd.com> Acked-by:
Stylon Wang <stylon.wang@amd.com> Signed-off-by:
Ian Chen <ian.chen@amd.com> Tested-by:
Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by:
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Wenjing Liu authored
[how] - Add minimial transition log with reason and base state. - Do not log set dpms interfaces for virtual signal in stream. Reviewed-by:
Dillon Varone <dillon.varone@amd.com> Acked-by:
Wenjing Liu <wenjing.liu@amd.com> Tested-by:
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Wenjing Liu authored
[why] During 8k video plane resizing we could transition from MPC combine mode back to ODM combine 2:1 + 8k video plane. In this transition minimal transition state is based on new state with ODM combine enabled. We are skipping this and it causes corruption because we have to reassign a current DPP pipe to a different MPC blending tree which is not supported seamlessly. Reviewed-by:
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Wenjing Liu authored
[why] ODM power optimization excludes subvp power optimization but subvp optimization can override ODM power optimization even if subvp optimization configuration is not found. This happens with 4k144hz + 1 5k desktop plane. We could have applied ODM power optimization however this is overridden by subvp but subvp ends up deciding not apply its optimization. [how] Move ODM power optimization decision after subvp so it will try ODM power optimization after subvp optimization is not possible. Reviewed-by:
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Wenjing Liu authored
[why] We have a few cases where we need to perform update topology update in dc update interface. However some of the updates are not seamless This could cause user noticible glitches. To enforce seamless transition we are adding a checking condition and error logging so the corruption as result of non seamless transition can be easily spotted. Reviewed-by:
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Aric Cyr authored
Acked-by:
Aric Cyr <aric.cyr@amd.com> Tested-by:
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Muhammad Ahmed authored
[What] MST now recognizes both connected displays Reviewed-by:
Charlene Liu <charlene.liu@amd.com> Acked-by:
Muhammad Ahmed <ahmed.ahmed@amd.com> Tested-by:
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Charlene Liu authored
[why] fix some non-initialized register mask and update golden setting Reviewed-by:
Duncan Ma <duncan.ma@amd.com> Acked-by:
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Austin Zheng authored
Why: vrr_active_fixed should also be checked when determining if DRR is in use How: Add check for vrr_active_fixed when allow_freesync and vrr_active_variable are also checked Reviewed-by:
Alvin Lee <alvin.lee2@amd.com> Acked-by:
Austin Zheng <austin.zheng@amd.com> Tested-by:
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Sridevi Arvindekar authored
[WHY&HOW] Code cleanup found in internal tests Reviewed-by:
Sridevi Arvindekar <Sridevi.Arvindekar@amd.com> Tested-by:
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Yifan Zhang authored
gc info usage misses type conversion. Acked-by:
Yifan Zhang <yifan1.zhang@amd.com> Reviewed-by:
Li Ma <li.ma@amd.com> Signed-off-by:
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Qingqing Zhuo authored
[Why & How] Some registers are never used in the driver but defined. Remove them. Reviewed-by:
Roman Li <roman.li@amd.com> Acked-by:
Qingqing Zhuo <qingqing.zhuo@amd.com> Tested-by:
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Dillon Varone authored
[WHY&HOW] Add support for programming dp dto via dccg. Reviewed-by:
Jun Lei <jun.lei@amd.com> Acked-by:
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Wenjing Liu authored
[why] Current dc update design has limitation to support transition from ODM combine to minimum transition to MPC combine state seamlessly at the capability boundary when MPO plane is resizing. This will require dc update high level refactor in order to remove the design limitation. The decision is to block such use case for existing products by limiting ODM power optimization support for only those surfaces within guaranteed viewport size. This will prevent us from transitioning to MPC combine state when ODM power optimization is enabled. Reviewed-by:
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Wenjing Liu authored
[why] In some cases such as 8k desktop surface with 144Hz timing, we decide to enable ODM power optimization but this surface doesn't have a minimum transition state. Therefore we cannot switch off ODM power optimization seamlessly This creates path depedency on ODM power optimization decision. i.e whether or not we should switch off ODM power optimization is dependent on if the transition to switch off ODM power optimization from current state is seamless. We don't desire a path dependent power optimization policy as it is too dynamic and difficult to maintain. [how] Attempt ODM power optimization only after we can validate new state without using pipe combine. Reviewed-by:
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Wenjing Liu authored
[why] The result of predict_pipe_split calculation is no longer used but the function is not removed. This will cause unnecessary calculation of pipe split prediction in every frame update. Reviewed-by:
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David Francis authored
The code in kfd_mqd_manager_v11.c to support criu dump and restore of queue state was missing. Added it; should be equivalent to kfd_mqd_manager_v10.c. CC: Felix Kuehling <felix.kuehling@amd.com> Reviewed-by:
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Aurabindo Pillai authored
[Why&How] For enabling automated testing, add a hook to DCHUBBUB interface so that mall status can be queried by userspace through debugfs. This removes dependence on requiring a userspace tool like UMR for querying status for MALL static screen IGT test. Reviewed-by:
Aurabindo Pillai <aurabindo.pillai@amd.com> Tested-by:
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