- 08 Oct, 2007 2 commits
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Kumar Gala authored
We now generate vdso[32,64].so.dbg as part of the build so add them to .gitignore Signed-off-by:Kumar Gala <galak@kernel.crashing.org>
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Kumar Gala authored
The PCI nodes on the MPC8568 dts didn't get moved up to be sibilings of the SOC node when we did that clean up for some reason. Fix that up and some minor whitespace and adjusting the size of the soc reg property. Signed-off-by:
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- 04 Oct, 2007 37 commits
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Anton Vorontsov authored
According to u-boot/board/mpc8568mds/init.S: LAW(Local Access Window) configuration: 2) 0xa000_0000 0xbfff_ffff PCIe MEM 512MB 4) 0xe280_0000 0xe2ff_ffff PCIe I/O 8M Signed-off-by:
Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by:
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Anton Vorontsov authored
MPC8568E-MDS have DS1374 chip on the I2C bus, thus let's use it. This patch also adds #address-cells and #size-cells to the I2C controllers nodes. p.s. DS1374 rtc class driver is in the -mm tree, its name is rtc-rtc-class-driver-for-the-ds1374.patch. Signed-off-by:
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Anton Vorontsov authored
i2c_board_info used semi-initialized, causing garbage in the info->flags, and that, in turn, causes various symptoms of i2c malfunctioning, like PEC mismatches. Signed-off-by:
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Scott Wood authored
The way the current CPM binding describes available multi-user (a.k.a. dual-ported) RAM doesn't work well when there are multiple free regions, and it doesn't work at all if the region doesn't begin at the start of the muram area (as the hardware needs to be programmed with offsets into this area). The latter situation can happen with SMC UARTs on CPM2, as its parameter RAM is relocatable, u-boot puts it at zero, and the kernel doesn't support moving it. It is now described with a muram node, similar to QE. The current CPM binding is sufficiently recent (i.e. never appeared in an official release) that compatibility with existing device trees is not an issue. The code supporting the new binding is shared between cpm1 and cpm2, rather than remain separated. QE should be able to use this code as well, once minor fixes are made to its device trees. Signed-off-by:
Scott Wood <scottwood@freescale.com> Signed-off-by:
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Kumar Gala authored
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Emil Medve authored
According to the publicly available MPC8360E RM (rev. 1 from 09/2006 and rev. 2 from 05/2007) and MPC8323E RM (rev. 1 from 09/2006), CEURNR is the QE microcode revision number register and is located at offset 0x1b8 within the QE internal register space Signed-off-by:
Emil Medve <Emilian.Medve@Freescale.com> Signed-off-by:
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Peter Korsgaard authored
Add support for the I2C devices handled by the rtc-ds1307 driver to of_register_i2c_devices. Cc: G. Liakhovetski <g.liakhovetski@gmx.de> Signed-off-by:
Peter Korsgaard <jacmet@sunsite.dk> Signed-off-by:
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Peter Korsgaard authored
Fix a trivial printk typo in fsl_soc. Cc: G. Liakhovetski <g.liakhovetski@gmx.de> Signed-off-by:
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Scott Wood authored
Previously, Soft_emulate_8xx was called with no implementation, resulting in build failures whenever building 8xx without math emulation. The implementation is copied from arch/ppc to resolve this issue. However, this sort of minimal emulation is not a very good idea other than for compatibility with existing userspaces, as it's less efficient than soft-float and can mislead users into believing they have soft-float. Thus, it is made a configurable option, off by default. Signed-off-by:
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Roy Zang authored
This patch adds cuboot support for MPC7448HPC2 platform. The cuImage can be used with legacy u-boot without FDT support. Signed-off-by:
Roy Zang <tie-fei.zang@freescale.com> Acked-by:
David Gibson <david@gibson.dropbear.id.au> Signed-off-by:
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Scott Wood authored
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Scott Wood authored
1. PCI and reset are factored out into pq2.c. I renamed them from m82xx to pq2 because they won't work on the Integrated Host Processor line of 82xx chips (i.e. 8240, 8245, and such). 2. The PCI PIC, which is nominally board-specific, is used on multiple boards, and thus is used into pq2ads-pci-pic.c. 3. The new CPM binding is used. 4. General cleanup. Signed-off-by:
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Scott Wood authored
This board is also resold by Freescale under the names "QUICCStart MPC885 Evaluation System" and "CWH-PPC-885XN-VE". Signed-off-by:
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Scott Wood authored
It now uses the new CPM binding and the generic pin/clock functions, and has assorted fixes and cleanup. Signed-off-by:
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Scott Wood authored
The localbus node is used to describe devices that are connected via a chip select or similar mechanism. The advantages over placing the devices under the root node are that it can be probed without probing other random things under the root, and that the description of which chip select a given device uses can be used to set up mappings if the firmware failed to do so in a useful manner. cuboot-pq2 is updated to match the binding; previously, it called itself chipselect rather than localbus, and used phandle linkage between the actual bus node and the control node (the current agreement is to simply use the fully-qualified address of the control registers, and ignore the overlap with the IMMR node). Signed-off-by:
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Scott Wood authored
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Scott Wood authored
This is just a rename patch; internal references to mpc82xx_ads will be changed in the next one. Signed-off-by:
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Scott Wood authored
m82xx_calibrate_decr(), mpc82xx_ads_show_cpuinfo(), and mpc82xx_halt() do anything useful beyond what the generic code does. Signed-off-by:
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Scott Wood authored
The 8272 (and presumably other PCI PQ2 chips) appear to have the same issue as the 83xx regarding PCI streaming DMA. Signed-off-by:
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Scott Wood authored
This provides a generic way for board code to set up CPM pins, rather than directly poking magic values into registers. Signed-off-by:
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Scott Wood authored
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Scott Wood authored
Mostly sparse fixes (__iomem annotations, etc); also, cpm2_immr is used rather than creating many temporary mappings. Signed-off-by:
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John Traill authored
The 8xx can only support a max of 8M during early boot (it seems a lot of 8xx boards only have 8M so the bug was never triggered), but the early allocator isn't aware of this. The following change makes it able to run with larger memory. Signed-off-by:
John Traill <john.traill@freescale.com> Signed-off-by:
Vitaly Bordug <vitb@kernel.crashing.org> Signed-off-by:
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Scott Wood authored
The CPU15 erratum on MPC8xx chips can cause incorrect code execution under certain circumstances, where there is a conditional or indirect branch in the last word of a page, with a target in the last cache line of the next page. This patch implements one of the suggested workarounds, by forcing a TLB miss whenever execution crosses a page boundary. This is done by invalidating the pages before and after the one being loaded into the TLB in the ITLB miss handler. Signed-off-by:
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Scott Wood authored
These let board code set up pins and clocks without having to put magic numbers directly into the registers. The clock function is mostly duplicated from the cpm2 version; hopefully this stuff can be merged at some point. Signed-off-by:
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Scott Wood authored
1. Keep a global mpc8xx_immr mapping, rather than constantly creating temporary mappings. 2. Look for new fsl,cpm1 and fsl,cpm1-pic names. 3. Always reset the CPM when not using the udbg console; this is required in case the firmware initialized a device that is incompatible with one that the kernel is about to use. 4. Remove some superfluous casts and header includes. 5. Change a usage of IMAP_ADDR to get_immrbase(). 6. Use phys_addr_t, not uint, for dpram_pbase. 7. Various sparse-related fixes, such as __iomem annotations. 8. Remove mpc8xx_show_cpuinfo, which doesn't provide anything useful beyond the generic cpuinfo handler. 9. Move prototypes for 8xx support functions from board files to sysdev/commproc.h. Signed-off-by:
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Scott Wood authored
1. Move CONSISTENT_START on 8xx so that it doesn't overlap the IMMR mapping. 2. The wrong register was being loaded into SPRN_MD_RPN. Signed-off-by:
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Scott Wood authored
This prevents some bootloader/bootwrapper characters from being lost. Signed-off-by:
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Scott Wood authored
Mostly a bunch of direct access to in/out conversions, plus a few cast removals, __iomem annotations, and miscellaneous cleanup. Signed-off-by:
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Scott Wood authored
The existing OF glue code was crufty and broken. Rather than fix it, it has been removed, and the serial driver now talks to the device tree directly. The non-CONFIG_PPC_CPM_NEW_BINDING code can go away once CPM platforms are dropped from arch/ppc (which will hopefully be soon), and existing arch/powerpc boards that I wasn't able to test on for this patchset get converted (which should be even sooner). Signed-off-by:
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Scott Wood authored
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Scott Wood authored
fsl_get_immr() uses /soc/ranges to determine the immr. mpc885_get_clock() transforms a crystal frequency into a system frequency according to the PLL register settings. pq2_get_clocks() does the same as the above for the PowerQUICC II, except that it produces several different clocks. The mpc8xx/pq2 set_clocks() functions modify common properties in the device tree based on the given clock data. The mpc885/pq2 fixup_clocks() functions call get_clocks(), and pass the results to set_clocks(). Signed-off-by:
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Scott Wood authored
Consensus was reached to put PCI nodes at the root of the tree (and not under /soc), but the phandle to a control node was rejected in favor of simply not worrying about /pci/reg overlapping /soc/ranges. This updates cuboot-82xx to not look for the phandle. Signed-off-by:
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Scott Wood authored
This code assumes that the ports have been previously set up, with buffers in DPRAM. Signed-off-by:
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Scott Wood authored
This introduces a new device binding for the CPM and other devices on these boards. Some of the changes include: 1. Proper namespace scoping for Freescale compatibles and properties. 2. Use compatible rather than things like device_type and model to determine which particular variant of a device is present. 3. Give the drivers the relevant CPM command word directly, rather than requiring it to have a lookup table based on device-id, SCC v. SMC, and CPM version. 4. Specify the CPCR and the usable DPRAM region in the CPM's reg property. Boards that do not require the legacy bindings should select CONFIG_PPC_CPM_NEW_BINDING to enable the of_platform CPM devices. Once all existing boards are converted and tested, the config option can become default y to prevent new boards from using the old model. Once arch/ppc is gone, the config option can be removed altogether. Signed-off-by:
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Scott Wood authored
As suggested by David Gibson, now that we have a separate node for the baud rate generators, it's better to use the standard clock-frequency property than a cpm-node-level fsl,brg-frequency property. This patch updates existing places where fsl,brg-frequency is used. Signed-off-by:
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Paul Mackerras authored
Commit 8112753b made 44x in ARCH=powerpc builds use cpu setup routines in cpu_setup_44x.S, but didn't make a similar change for ARCH=ppc, and consequently the ARCH=ppc builds fail with undefined symbols (since both use the same cputable.c). This fixes it by including cpu_setup_44x.S in the ARCH=ppc builds, and by taking out the now-redundant FPU initialization in arch/ppc/kernel/head_44x.S. Signed-off-by:
Paul Mackerras <paulus@samba.org>
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- 03 Oct, 2007 1 commit
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Grant Likely authored
Reverts commit a15da8ef This driver is used by devices other than the xilinx opb-uartlite which depend on bytewise access to the registers. The change to 32 bit access does not work on these devices. Signed-off-by:
Grant Likely <grant.likely@secretlab.ca> Acked-by:
Josh Boyer <jwboyer@linux.vnet.ibm.com>
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