- 13 Oct, 2023 32 commits
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Asad Kamal authored
Expose ras table version & schema info to sysfs v2: Updated schema to get poison support info from ras context, removed asic specific checks Signed-off-by:
Asad Kamal <asad.kamal@amd.com> Reviewed-by:
Lijo Lazar <lijo.lazar@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Lijo Lazar authored
PSP OS updates the version information in register. On APUs with PSPv13, PSP OS will already be loaded with SBIOS. Hence use the version register instead of using information in driver binary header. Signed-off-by:
Yang Wang <kevinyang.wang@amd.com> Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
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Bob Zhou authored
Recently, the driver introduce DML2 for future ASIC support. But, some ASIC's hubbub pointer is null before calling. It cause the below null pointer issue, so add null check to fix it. BUG: kernel NULL pointer dereference, address: 0000000000000000 RIP: 0010:dc_create_resource_pool+0xc1/0x2c0 [amdgpu] Call Trace: <TASK> ? show_regs.cold+0x1a/0x1f ? __die_body+0x20/0x70 ? __die+0x2b/0x37 ? page_fault_oops+0x136/0x2c0 ? do_user_addr_fault+0x303/0x660 ? exc_page_fault+0x77/0x170 ? asm_exc_page_fault+0x27/0x30 ? dc_create_resource_pool+0xc1/0x2c0 [amdgpu] ? dc_create_resource_pool+0x243/0x2c0 [amdgpu] dc_create+0x23f/0x6b0 [amdgpu] ? dmi_matches+0xa3/0x200 amdgpu_dm_init+0x2bd/0x22a0 [amdgpu] Fixes: 7966f319 ("drm/amd/display: Introduce DML2") Signed-off-by:
Bob Zhou <bob.zhou@amd.com> Acked-by:
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Lang Yu authored
Program vcn_doorbell_range with vcn_ring0_1. Signed-off-by:
Lang Yu <Lang.Yu@amd.com> Reviewed-by:
Veerabadhran Gopalakrishnan <Veerabadhran.Gopalakrishnan@amd.com> Signed-off-by:
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Mario Limonciello authored
As dc_set_power_state() no longer allocates memory, it's not necessary to have return types and check return code as it can't fail anymore. Change it back to `void`. Reviewed-by:
Mario Limonciello <mario.limonciello@amd.com> Signed-off-by:
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Mario Limonciello authored
If there is memory pressure at suspend time then dynamically allocating a large structure as part of DC suspend code will fail. Instead re-use the same structures and clear all members except those that should be maintained. Link: https://gitlab.freedesktop.org/drm/amd/-/issues/2362Acked-by:
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Mario Limonciello authored
drm_atomic_helper_suspend() can return PTR_ERR(), in which case the error gets stored into `dm->cached_state`. This can cause failures during resume. Catch the error during suspend and fail the suspend instead. Link: https://gitlab.freedesktop.org/drm/amd/-/issues/2362Acked-by:
Christian König <christian.koenig@amd.com> Acked-by:
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Mario Limonciello authored
amdgpu_uvd_suspend() allocates memory and copies objects into that allocated memory. This fails under memory pressure. Instead move majority of this code into a prepare step when swap can still be allocated. Reviewed-by:
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Mario Limonciello authored
If any IP blocks allocate memory during their hw_fini() sequence this can cause the suspend to fail under memory pressure. Introduce a new phase that IP blocks can use to allocate memory before suspend starts so that it can potentially be evicted into swap instead. Reviewed-by:
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Mario Limonciello authored
Linux PM core has a prepare() callback run before suspend. If the system is under high memory pressure, the resources may need to be evicted into swap instead. If the storage backing for swap is offlined during the suspend() step then such a call may fail. So move this step into prepare() to move evict majority of resources and update all non-pmops callers to call the same callback. Link: https://gitlab.freedesktop.org/drm/amd/-/issues/2362Reviewed-by:
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Li Ma authored
Add CG support for GFX/MC/HDP/ATHUB/IH/BIF. Add PG support for GFX. Signed-off-by:
Li Ma <li.ma@amd.com> Signed-off-by:
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Lang Yu authored
Power up/down UMSCH by SMU. Signed-off-by:
Leo Liu <leo.liu@amd.com> Acked-by:
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Lang Yu authored
Add ppt callback to power up/down UMSCH. v2: squash in updates (Alex) Signed-off-by:
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Lang Yu authored
Powerup VPE by SMU. Signed-off-by:
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Li Ma authored
add smu 14 into the IP discovery list. Signed-off-by:
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Kenneth Feng authored
Add initial swSMU support for smu 14 series ASIC. v2: squash in build fixes and updates (Li Ma) fix warnings (Alex) v3: squash in updates (Alex) v4: squash in updates (Alex) v5: squash in avg/current power updates (Alex) Signed-off-by:Kenneth Feng <kenneth.feng@amd.com> Signed-off-by:
Likun Gao <Likun.Gao@amd.com> Signed-off-by:
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Li Ma authored
Add initial smu v14_0_0 pmfw if file v2: squash in updates (Alex) Signed-off-by:
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Li Ma authored
Add initial smu v14_0_0 ppsmc file v2: squash in updates (Alex) v3: squash in updates (Alex) Signed-off-by:
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Li Ma authored
Add initial smu v14_0_0 driver if file v2: squash in updates (Alex) v3: update interface (Alex) Signed-off-by:
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Lang Yu authored
VCN 4.0.5 uses DLDO. Signed-off-by:
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Lang Yu authored
These changes are missed in rebase. Signed-off-by:
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Lijo Lazar authored
IP discovery region has increased to > 8K on some SOCs.Maximum reserve size is upto 12K, but not used. For now increase to 10K. Signed-off-by:
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Asad Kamal authored
Use gpu_metrics_v1_4 for SMUv13.0.6 to fill gpu metric info v3: Removed filling gpu metric instantaneous pcie bw Signed-off-by:
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Asad Kamal authored
Add new gpu_metrics_v1_4 to acquire XGMI data transfer, pcie bandwidth & Clock lock status v2: Add pcie error counter to gpu metric table v1_4 Signed-off-by:
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Asad Kamal authored
Update pmfw metric table to include xgmi transfer data and pci instantaneous bandwidth for smu v13_0_6 v2: Updated metric table version v3: Removed inst pcie bw with alignment to metrics table version 8 Signed-off-by:
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Lin.Cao authored
Return -EINVAL when MMSCH init fail which can be handle by function amdgpu_device_reset_sriov correctly. Signed-off-by:
Lin.Cao <lincao12@amd.com> Reviewed-by:
Jingwen Chen <Jingwen.Chen2@amd.com> Signed-off-by:
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Tim Huang authored
Wait for completion of sending the EnableGfxImu message when using the PSP FW loading. Signed-off-by:
Tim Huang <Tim.Huang@amd.com> Reviewed-by:
Yifan Zhang <yifan1.zhang@amd.com> Signed-off-by:
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Lang Yu authored
Avoid infinite loop when count is 0. This is missed in rebase. Signed-off-by:
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Srinivasan Shanmugam authored
Fixes the below: drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c:274: warning: Function parameter or member 'gart_placement' not described in 'amdgpu_gmc_gart_location' Cc: Christian König <christian.koenig@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: "Pan, Xinhui" <Xinhui.Pan@amd.com> Signed-off-by:
Srinivasan Shanmugam <srinivasan.shanmugam@amd.com> Reviewed-by:
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Lang Yu authored
MCBP is decided by adev->gfx.mcbp now. This is missed in rebase. Signed-off-by:
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Lang Yu authored
Remove IB end boundary requirement, VPE has no such limitions, use existing amdgpu_ring_generic_pad_ib() instead. This is missed in rebase. Signed-off-by:
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Jay Cornwall authored
When MES is oversubscribed it may not frequently check for new command submissions from driver if the scheduling load is high. Response latency as high as 5 seconds has been observed. Enable a flag which adds a check for new commands between scheduling quantums. Signed-off-by:
Jay Cornwall <jay.cornwall@amd.com> Cc: Alexandru Tudor <alexandru.tudor@amd.com> Reviewed-by:
Harish Kasiviswanathan <Harish.Kasiviswanathan@amd.com> Signed-off-by:
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- 09 Oct, 2023 8 commits
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Icenowy Zheng authored
SI hardware does not have doorbells at all, however currently the code will try to do the allocation and thus fail, makes SI AMDGPU not usable. Fix this failure by skipping doorbells allocation when doorbells count is zero. Fixes: 54c30d2a ("drm/amdgpu: create kernel doorbell pages") Reviewed-by:
Shashank Sharma <shashank.sharma@amd.com> Signed-off-by:
Icenowy Zheng <uwu@icenowy.me> Signed-off-by:
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Aaron Liu authored
Enable DCN 3.5.0 support. Signed-off-by:
Aaron Liu <aaron.liu@amd.com> Signed-off-by:
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Arvind Yadav authored
Here, Adding db_size in byte to find the doorbell's absolute offset for both 32-bit and 64-bit doorbell sizes. So that doorbell offset will be aligned based on the doorbell size. v2: - Addressed the review comment from Felix. v3: - Adding doorbell_size as parameter to get db absolute offset. v4: Squash the two patches into one. Cc: Christian Koenig <christian.koenig@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Reviewed-by:
Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by:
Arvind Yadav <Arvind.Yadav@amd.com> Signed-off-by:
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Christian König authored
bo->tbo.resource can easily be NULL here. Link: https://gitlab.freedesktop.org/drm/amd/-/issues/2902Signed-off-by:
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Aric Cyr authored
This version brings along following fixes: - Refactor DPG test pattern logic for ODM cases - Refactor HWSS into component folder - Revert "drm/amd/display: Add a check for idle power optimization" - Revert "drm/amd/display: remove duplicated edp relink to fastboot - Update cursor limits based on SW cursor fallback limits - Update stream mask - Update pmfw_driver_if new structure - Modify SMU message logs - Don't set dpms_off for seamless boot Known issue: DWB (Writeback functionality) is broken. Fix will be available in DC 3.2.256 Acked-by:
Tom Chung <chiahsuan.chung@amd.com> Signed-off-by:
Aric Cyr <aric.cyr@amd.com> Tested-by:
Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by:
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Stylon Wang authored
[Why] This could work around the issue with DP tunneling producing a NULL pointer dereference. [How] Disable the virtual links. Reviewed-by:
Stylon Wang <stylon.wang@amd.com> Tested-by:
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George Shen authored
[Why] Enabling DPG causes HUBP to stay in blank constantly. If DPG is enabled while an MCLK switch is taking place with SubVP, it will cause the MCLK to never complete. This is because SubVP MCLK switch relies a HUBP VLine interrupt, which will never occur when HUBP is constantly in blank. [How] Disable SubVP when test pattern is enabled. Reviewed-by:
Alvin Lee <alvin.lee2@amd.com> Reviewed-by:
Nevenko Stupar <nevenko.stupar@amd.com> Acked-by:
George Shen <george.shen@amd.com> Tested-by:
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George Shen authored
[Why] Current DPG test pattern logic does not account for ODM configuration changes after test pattern has already been programmed. For example, if ODM2:1 is enabled after test pattern is already being output, the second pipe is not programmed to output test pattern, causing half the screen to be black. [How] Move DPG test pattern parameter calculations into separate function. Whenever ODM pipe configuration changes, re-calculate DPG test pattern parameters and program DPG if test pattern is currently enabled. Reviewed-by:
Wenjing Liu <wenjing.liu@amd.com> Acked-by:
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