- 30 Jan, 2008 40 commits
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Joerg Roedel authored
This lets SVM ignore writes of the value 0 to the performance counter control registers. Thus enabling them will still fail in the guest, but a write of 0 which keeps them disabled is accepted. This is required to boot Windows Vista 64bit. [avi: avoid fall-thru in switch statement] Signed-off-by:
Joerg Roedel <joerg.roedel@amd.com> Signed-off-by:
Markus Rechberger <markus.rechberger@amd.com> Signed-off-by:
Avi Kivity <avi@qumranet.com>
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Joerg Roedel authored
This patch fixes a compile error of the LAPIC code with APIC debugging enabled. Signed-off-by:
Joerg Roedel <joerg.roedel@amd.com> Signed-off-by:
Markus Rechberger <markus.rechberger@amd.com> Signed-off-by:
Avi Kivity <avi@qumranet.com>
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Marcelo Tosatti authored
There is a race where VCPU0 is shadowing a pagetable entry while VCPU1 is updating it, which results in a stale shadow copy. Fix that by comparing the contents of the cached guest pte with the current guest pte after write-protecting the guest pagetable. Signed-off-by:
Marcelo Tosatti <mtosatti@redhat.com> Signed-off-by:
Avi Kivity <avi@qumranet.com>
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Joerg Roedel authored
With this patch KVM on SVM will exit to userspace if the guest writes to CR8 and the in-kernel APIC is disabled. Signed-off-by:
Joerg Roedel <joerg.roedel@amd.com> Signed-off-by:
Markus Rechberger <markus.rechberger@amd.com> Signed-off-by:
Avi Kivity <avi@qumranet.com>
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Avi Kivity authored
In addition to removing some duplicated code, this also handles the unlikely case of real-mode code updating a guest page table. This can happen when one vcpu (in real mode) touches a second vcpu's (in protected mode) page tables, or if a vcpu switches to real mode, touches page tables, and switches back. Signed-off-by:
Avi Kivity <avi@qumranet.com>
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Avi Kivity authored
Signed-off-by:
Avi Kivity <avi@qumranet.com>
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Avi Kivity authored
As set_pte() no longer references either a gpte or the guest walker, we can move it out of paging mode dependent code (which compiles twice and is generally nasty). Signed-off-by:
Avi Kivity <avi@qumranet.com>
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Avi Kivity authored
Unused. Signed-off-by:
Avi Kivity <avi@qumranet.com>
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Avi Kivity authored
This allows us to remove its dependency on pt_element_t. Signed-off-by:
Avi Kivity <avi@qumranet.com>
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Avi Kivity authored
We already set it according to cumulative access permissions. Signed-off-by:
Avi Kivity <avi@qumranet.com>
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Avi Kivity authored
When we emulate a guest pte write, we fail to apply the correct inherited permissions from the parent ptes. Now that we store inherited permissions in the shadow page, we can use that to update the pte permissions correctly. Signed-off-by:
Avi Kivity <avi@qumranet.com>
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Avi Kivity authored
Signed-off-by:
Avi Kivity <avi@qumranet.com>
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Avi Kivity authored
While the page table walker correctly generates a guest page fault if a guest tries to execute a non-executable page, the shadow code does not mark it non-executable. This means that if a guest accesses an nx page first with a read access, then subsequent code fetch accesses will succeed. Fix by setting the nx bit on shadow ptes. Signed-off-by:
Avi Kivity <avi@qumranet.com>
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Avi Kivity authored
The nx bit is awkwardly placed in the 63rd bit position; furthermore it has a reversed meaning compared to the other bits, which means we can't use a bitwise and to calculate compounded access masks. So, we simplify things by creating a new 3-bit exec/write/user access word, and doing all calculations in that. Signed-off-by:
Avi Kivity <avi@qumranet.com>
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Marcelo Tosatti authored
In preparation for multi-threaded guest pte walking, use cmpxchg() when updating guest pte's. This guarantees that the assignment of the dirty bit can't be lost if two CPU's are faulting the same address simultaneously. [avi: fix kunmap_atomic() parameters] Signed-off-by:
Marcelo Tosatti <mtosatti@redhat.com> Signed-off-by:
Avi Kivity <avi@qumranet.com>
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Avi Kivity authored
Later we may be able to use the virtual tpr feature, but for now, just trap it. Signed-off-by:
Avi Kivity <avi@qumranet.com>
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Avi Kivity authored
Stack instructions are always 64-bit on 64-bit mode; many of the emulated stack instructions did not take that into account. Fix by adding a 'Stack' bitflag and setting the operand size appropriately during the decode stage (except for 'push r/m', which is in a group with a few other instructions, so it gets its own treatment). This fixes random crashes on Vista x64. Signed-off-by:
Avi Kivity <avi@qumranet.com>
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Joerg Roedel authored
This patch adds code to emulate the access to the cr8 register to the x86 instruction emulator in kvm. This is needed on svm, where there is no hardware decode for control register access. Signed-off-by:
Joerg Roedel <joerg.roedel@amd.com> Signed-off-by:
Markus Rechberger <markus.rechberger@amd.com> Signed-off-by:
Avi Kivity <avi@qumranet.com>
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Avi Kivity authored
With apic in userspace, we must exit to userspace after a cr8 write in order to update the tpr. But if the apic is in the kernel, the exit is unnecessary. Noticed by Joerg Roedel. Signed-off-by:
Avi Kivity <avi@qumranet.com>
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Avi Kivity authored
We prepare eflags for the emulated instruction, then clobber it with an 'andl'. Fix by popping eflags as the last thing in the sequence. Patch taken from Xen (16143:959b4b92b6bf) Signed-off-by:
Avi Kivity <avi@qumranet.com>
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Avi Kivity authored
Signed-off-by:
Avi Kivity <avi@qumranet.com>
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Avi Kivity authored
Signed-off-by:
Avi Kivity <avi@qumranet.com>
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Avi Kivity authored
Signed-off-by:
Avi Kivity <avi@qumranet.com>
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Avi Kivity authored
Instead of each subarch doing its own thing, add an API for queuing an injection, and manage failed exception injection centerally (i.e., if an inject failed due to a shadow page fault, we need to requeue it). Signed-off-by:
Avi Kivity <avi@qumranet.com>
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Marcelo Tosatti authored
Signed-off-by:
Marcelo Tosatti <mtosatti@redhat.com> Signed-off-by:
Avi Kivity <avi@qumranet.com>
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npiggin@suse.de authored
Signed-off-by:
Nick Piggin <npiggin@suse.de> Cc: kvm-devel@lists.sourceforge.net Cc: avi@qumranet.com Cc: linux-kernel@vger.kernel.org Signed-off-by:
Avi Kivity <avi@qumranet.com>
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Hollis Blanchard authored
This abstracts the detail of x86 hlt and INIT modes into a function. Signed-off-by:
Hollis Blanchard <hollisb@us.ibm.com> Acked-by:
Carsten Otte <cotte@de.ibm.com> Signed-off-by:
Avi Kivity <avi@qumranet.com>
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Hollis Blanchard authored
Signed-off-by:
Hollis Blanchard <hollisb@us.ibm.com> Signed-off-by:
Avi Kivity <avi@qumranet.com>
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Hollis Blanchard authored
Signed-off-by:
Hollis Blanchard <hollisb@us.ibm.com> Acked-by:
Carsten Otte <cotte@de.ibm.com> Signed-off-by:
Avi Kivity <avi@qumranet.com>
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Hollis Blanchard authored
Signed-off-by:
Hollis Blanchard <hollisb@us.ibm.com> Acked-by:
Carsten Otte <cotte@de.ibm.com> Signed-off-by:
Avi Kivity <avi@qumranet.com>
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Zhang Xiantao authored
iosapic supports an additional mmio EOI register compared to ioapic. Signed-off-by:
Zhang Xiantao <xiantao.zhang@intel.com> Signed-off-by:
Avi Kivity <avi@qumranet.com>
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Zhang Xiantao authored
Change dest_Loest_Prio -> IOAPIC_LOWEST_PRIORITY dest_Fixed -> IOAPIC_FIXED the original names are x86 specific, while the ioapic code will be reused for ia64. Signed-off-by:
Zhang Xiantao <xiantao.zhang@intel.com> Signed-off-by:
Avi Kivity <avi@qumranet.com>
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Zhang Xiantao authored
This patch replaces lapic structure with kvm_vcpu in ioapic.c, making ioapic independent of the local apic, as required by ia64. Signed-off-by:
Zhang Xiantao <xiantao.zhang@intel.com> Signed-off-by:
Avi Kivity <avi@qumranet.com>
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Carlo Marcelo Arenas Belon authored
This patch removes the KVM specific defines for MSR_EFER that were being used in the svm support file and migrates all references to use instead the ones from the kernel headers that are used everywhere else and that have the same values. Signed-off-by:
Carlo Marcelo Arenas Belon <carenas@sajinet.com.pe> Signed-off-by:
Avi Kivity <avi@qumranet.com>
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Avi Kivity authored
Currently, make headers_check barfs due to <asm/kvm.h>, which <linux/kvm.h> includes, not existing. Rather than add a zillion <asm/kvm.h>s, export kvm.h only if the arch actually supports it. Signed-off-by:
Avi Kivity <avi@qumranet.com>
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Zhang Xiantao authored
Signed-off-by:
Zhang Xiantao <xiantao.zhang@intel.com> Signed-off-by:
Avi Kivity <avi@qumranet.com>
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Zhang Xiantao authored
Other archs doesn't need it. Signed-off-by:
Zhang Xiantao <xiantao.zhang@intel.com> Signed-off-by:
Avi Kivity <avi@qumranet.com>
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Avi Kivity authored
Unify the special instruction switch with the regular instruction switch, and the two byte special instruction switch with the regular two byte instruction switch. That makes it much easier to find an instruction or the place an instruction needs to be added in. Signed-off-by:
Avi Kivity <avi@qumranet.com>
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Avi Kivity authored
The rep prefix cleanup left two switch () statements next to each other. Unify them. Signed-off-by:
Avi Kivity <avi@qumranet.com>
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Avi Kivity authored
Currently rep processing is handled somewhere in the middle of instruction processing. Move it to a sensible place. Signed-off-by:
Avi Kivity <avi@qumranet.com>
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