- 26 Feb, 2024 13 commits
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Connor Abbott authored
Use the vendor-provided snapshot headers to dump the contextless registers, shader blocks, and cluster registers. Still unimplemented are the GMU registers and "external core" registers, which would require more work because they use register spaces we don't have described in devicetree and dump registers from multiple spaces in a single list. Signed-off-by:
Connor Abbott <cwabbott0@gmail.com> Patchwork: https://patchwork.freedesktop.org/patch/575919/Signed-off-by:
Rob Clark <robdclark@chromium.org>
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Connor Abbott authored
We were overwriting the last indexed reg (CP_ROQ) and we were snapshotting the same CP_MEMPOOL block twice instead of snapshotting CP_BV_MEMPOOL as intended. Signed-off-by:
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Connor Abbott authored
This imports these files as-is, the following commits will have to make slight changes to get them to compile because downstream uses un-namespaced enums that conflict with a6xx. However we should try as much as possible to stick to downstream's format to make importing new gens easier. Signed-off-by:
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Neil Armstrong authored
Add support for the A750 GPU found on the SM8650 platform Unlike the the very close A740 GPU on the SM8550 SoC, the A750 GPU doesn't have an HWCFG block but a separate register set. The A750 GPU info are added under the adreno_is_a750() macro and the ADRENO_7XX_GEN3 family id. Reviewed-by:
Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by:
Neil Armstrong <neil.armstrong@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/578693/Signed-off-by:
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Neil Armstrong authored
Document the GPU SMMU found on the SM8650 platform. Signed-off-by:
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/578685/Signed-off-by:
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Neil Armstrong authored
The if condition for the SM8[45]50 GPU SMMU is too large, add the other compatible strings to the condition to only allow the clocks for the GPU SMMU nodes. Fixes: 4fff78dc ("dt-bindings: arm-smmu: Document SM8[45]50 GPU SMMU") Suggested-by:
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by:
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Neil Armstrong authored
Document the Adreno 750 GMU found on the SM8650 platform. Reviewed-by:
Conor Dooley <conor.dooley@microchip.com> Signed-off-by:
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Luca Weiss authored
Add support for the Adreno 305B GPU that is found in MSM8226(v2) SoC. Previously this was mistakenly claimed to be supported but using wrong a configuration. In MSM8226v1 there's also a A305B but with chipid 0x03000510 which should work with the same configuration but due to lack of hardware for testing this is not added. Reviewed-by:
Luca Weiss <luca@z3ntu.xyz> Reviewed-by:
David Heidelberg <david@ixit.cz> Patchwork: https://patchwork.freedesktop.org/patch/575274/Signed-off-by:
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Luca Weiss authored
Some GPUs like the Adreno A305B has a patchid higher than 9, in this case 18. Make sure the regexes can account for that. Acked-by:
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Rob Clark authored
We'd miss actually activating LLC. Signed-off-by:
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Rob Clark authored
This updates the GPU headers to latest from mesa, using gen_header.py (which is used to generate headers at bulid time for mesa), rather than headergen2 (which doesn't have proper support for A6XX vs A7XX register variants). Mostly just uninteresting churn, but there are a couple spots in a7xx paths which update REG_A6XX_foo to REG_A7XX_foo for registers which are a7xx specific. Cc: Connor Abbott <cwabbott0@gmail.com> Signed-off-by:
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Danila Tikhonov authored
SM7150 has 5 power levels which correspond to 5 speed-bin values: 0, 128, 146, 167, 172. Speed-bin value is calulated as FMAX/4.8MHz round up to zero decimal places. Also a618 on SM7150 uses a615 zapfw. Add a squashed version (.mbn). Add this as machine = "qcom,sm7150", because speed-bin values are different from atoll (sc7180/sm7125). Signed-off-by:
Danila Tikhonov <danila@jiaxyga.com> Reviewed-by:
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Dmitry Baryshkov authored
Historically the Adreno driver has not been updating memory configuration registers on a618 (SC7180 platform) implying that the default configuration is fine. After the rework performed in the commit 8814455a ("drm/msm: Refactor UBWC config setting") the function a6xx_calc_ubwc_config() still contained this shortcut and did not calculate UBWC configuration. However the function which now actually updates hardware registers, a6xx_set_ubwc_config(), doesn't contain such check. Rather than adding the check to a6xx_set_ubwc_config(), fill in the UBWC config for a618 (based on readings from SC7180). Reported-by:
Leonard Lausen <leonard@lausen.nl> Link: https://gitlab.freedesktop.org/drm/msm/-/issues/49 Fixes: 8814455a ("drm/msm: Refactor UBWC config setting") Cc: Connor Abbott <cwabbott0@gmail.com> Signed-off-by:
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- 22 Feb, 2024 4 commits
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Abel Vesa authored
Add definitions for the display hardware used on the Qualcomm X1E80100 platform. Co-developed-by:
Abhinav Kumar <quic_abhinavk@quicinc.com> Signed-off-by:
Abel Vesa <abel.vesa@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/579075/ Link: https://lore.kernel.org/r/20240220-x1e80100-display-v4-4-971afd9de861@linaro.orgSigned-off-by:
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Abel Vesa authored
Add support for MDSS on X1E80100. Reviewed-by:
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Abel Vesa authored
Document the MDSS hardware found on the Qualcomm X1E80100 platform. Reviewed-by:
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Abel Vesa authored
Document the DPU for Qualcomm X1E80100 platform in the SM8650 schema, as they are similar. Reviewed-by:
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- 19 Feb, 2024 9 commits
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Dmitry Baryshkov authored
Since the commit b962a120 ("drm/atomic: integrate modeset lock with private objects") the DRM framework no longer requires the external lock for private objects. Drop the lock, letting the DRM to manage private object locking. Signed-off-by:
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Dmitry Baryshkov authored
The Shared Memory Pool (SMP) state is a part of the MDP5's private object state. Use existing infrastructure, atomic_print_state() callback, to dump SMP state (which also makes it included into debugfs/dri/N/state). This allows us to drop the custom debugfs file too. Signed-off-by:
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Dmitry Baryshkov authored
Since the commit b962a120 ("drm/atomic: integrate modeset lock with private objects") the DRM framework no longer requires the external lock for private objects. Drop the lock, letting the DRM to manage private object locking. Signed-off-by:
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Dmitry Baryshkov authored
Add calls to finalise global state object and corresponding lock. Fixes: de3916c7 ("drm/msm/dpu: Track resources in global state") Signed-off-by:
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Dmitry Baryshkov authored
Bring in hardware support for the SDM660 and SDM630 platforms, which belong to the same DPU generation as MSM8998. Note, by default these platforms are still handled by the MDP5 driver unless the `msm.prefer_mdp5=false' parameter is provided. Co-developed-by:
Konrad Dybcio <konrad.dybcio@somainline.org> Signed-off-by:
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Dmitry Baryshkov authored
For some of the platforms (e.g. SDM660, SDM630, MSM8996, etc.) it is possible to support this platform via the DPU driver (e.g. to provide support for DP, multirect, etc). Add a modparam to be able to switch between these two drivers. All platforms supported by both drivers are by default handled by the MDP5 driver. To let them be handled by the DPU driver pass the `msm.prefer_mdp5=false` kernel param. Reviewed-by:
Stephen Boyd <swboyd@chromium.org> Reviewed-by:
Carl Vanderlip <quic_carlv@quicinc.com> Reviewed-by:
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Dmitry Baryshkov authored
Existing MDP5 devices have slightly different bindings. The main register region is called `mdp_phys' instead of `mdp'. Also vbif register regions are a part of the parent, MDSS device. Add support for handling this binding differences. Signed-off-by:
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Dmitry Baryshkov authored
Older (mdp5) platforms do not use per-SoC compatible strings. Instead they use a single compat entry 'qcom,mdss'. To facilitate migrating these platforms to the DPU driver provide a way to generate the MDSS / UBWC data at runtime, when the DPU driver asks for it. It is not possible to generate this data structure at the probe time, since some platforms might not have MDP_CLK enabled, which makes reading HW_REV register useless and prone to possible crashes. Signed-off-by:
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Colin Ian King authored
There is a spelling mistake in a drm_dbg_dp message. Fix it. Signed-off-by:
Colin Ian King <colin.i.king@gmail.com> Reviewed-by:
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- 11 Feb, 2024 14 commits
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Dmitry Baryshkov authored
Provide actual documentation for the pclk and hdisplay calculations in the case of DSC compression being used. Signed-off-by:
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Dmitry Baryshkov authored
Writeback was the last user of dpu_encoder_phys_ops's atomic_check() callback. As the code was moved to the dpu_writeback.c, the callback becomes unused. Drop it now. Reviewed-by:
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Dmitry Baryshkov authored
dpu_encoder_phys_wb is the only user of encoder's atomic_check callback. Move corresponding checks to drm_writeback_connector's implementation and drop the dpu_encoder_phys_wb_atomic_check() function. Signed-off-by:
Paloma Arellano <quic_parellan@quicinc.com> Patchwork: https://patchwork.freedesktop.org/patch/577524/ Link: https://lore.kernel.org/r/20240208-fd_remove_phys_ops_atomic_mode_set-v4-4-caf5dcd125c0@linaro.org
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Dmitry Baryshkov authored
The atomic_mode_set() callback only sets the phys_enc's IRQ data. As the INTF and WB are statically allocated to each encoder/phys_enc, drop the atomic_mode_set callback and set the IRQs during encoder init. For the CMD panel usecase some of IRQ indexes depend on the selected resources. Move setting them to the irq_enable() callback. Reviewed-by:
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Dmitry Baryshkov authored
Follow the _dpu_encoder_irq_control() change and split the _dpu_encoder_resource_control_helper() into enable and disable parts. Reviewed-by:
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Dmitry Baryshkov authored
The single helper for both enable and disable cases is too complicated, especially if we start adding more code to these helpers. Split it into irq_enable and irq_disable cases. Reviewed-by:
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Marijn Suijten authored
When the topology calls for two interfaces on the current fixed topology of 2 DSC blocks, or uses 1 DSC block for a single interface (e.g. SC7280 with only one DSC block), there should be no merging of DSC output. This is already represented by the return value of dpu_encoder_use_dsc_merge(), but not yet used to correctly configure this flag. Fixes: 58dca981 ("drm/msm/disp/dpu1: Add support for DSC in encoder") Signed-off-by:
Marijn Suijten <marijn.suijten@somainline.org> Reviewed-by:
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Marijn Suijten authored
drm_mipi_dsi.h already provides a conversion function from MIPI_DSI_FMT_ to bpp, named mipi_dsi_pixel_format_to_bpp(). Signed-off-by:
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Rob Herring authored
In order to check schemas for missing additionalProperties or unevaluatedProperties, cases allowing extra properties must be explicit. Signed-off-by:
Rob Herring <robh@kernel.org> Reviewed-by:
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Abhinav Kumar authored
Currently INTF_CFG2_DATA_HCTL_EN is coupled with the enablement of widebus but this is incorrect because we should be enabling this bit independent of widebus except for cases where compression is enabled in one pixel per clock mode. Fix this by making the condition checks more explicit and enabling INTF_CFG2_DATA_HCTL_EN for all other cases when supported by DPU. Fixes: 3309a756 ("drm/msm/dpu: revise timing engine programming to support widebus feature") Suggested-by:
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Dmitry Baryshkov authored
Finally drop separate "parsing" submodule. There is no need in it anymore. All submodules handle DT properties directly rather than passing them via the separate structure pointer. Signed-off-by:
Kuogee Hsieh <quic_khsieh@quicinc.com> Reviewed-by:
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Dmitry Baryshkov authored
Remove two levels of indirection and fetch next bridge directly in dp_display_probe_tail(). Signed-off-by:
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Dmitry Baryshkov authored
Instead of passing link properties through the separate struct, parse them directly in the dp_panel. Signed-off-by:
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Dmitry Baryshkov authored
Rather than parsing the I/O addresses from dp_parser and then passing them via a struct pointer to dp_catalog, handle I/O region parsing in dp_catalog and drop it from dp_parser. Signed-off-by:
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