- 06 Dec, 2022 9 commits
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Bjorn Andersson authored
Add the two bwmon instances and define votes for CPU -> LLCC and LLCC -> DDR, with bandwidth values based on the downstream DeviceTree. Signed-off-by:
Bjorn Andersson <quic_bjorande@quicinc.com> Reviewed-by:
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Tested-by:
Steev Klimaszewski <steev@kali.org> Reviewed-by:
Sibi Sankar <quic_sibis@quicinc.com> Signed-off-by:
Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221111032515.3460-11-quic_bjorande@quicinc.com
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Bjorn Andersson authored
Add the L3 interconnect path to all CPUs and define the bandwidth requirements for all opp entries across sc8280xp and sa8540p. The values are based on the tables reported by the hardware, distributed such that each value is the largest value, lower than the cluster frequency. Signed-off-by:
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Bjorn Andersson authored
Add a device node for the EPSS L3 frequency domain. Signed-off-by:
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Bjorn Andersson authored
Update all references to OSM or EPSS L3 compatibles, to include the generic compatible, as defined by the updated binding. Signed-off-by:
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Johan Hovold authored
Update the UFS PHY nodes to match the new binding. Signed-off-by:
Johan Hovold <johan+linaro@kernel.org> Reviewed-by:
Brian Masney <bmasney@redhat.com> Reviewed-by:
Konrad Dybcio <konrad.dybcio@somainline.org> Signed-off-by:
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Christian Marangi authored
This is not a fix on its own but more a cleanup. Phy qmp pcie driver currently have a workaround to handle pcs_misc not declared and add 0x400 offset to the pcs reg if pcs_misc is not declared. Correctly declare pcs_misc reg and reduce PCS size to the common value of 0x1f0 as done for every other qmp based pcie phy device. Signed-off-by:
Christian Marangi <ansuelsmth@gmail.com> Reviewed-by:
Vinod Koul <vkoul@kernel.org> Signed-off-by:
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Nícolas F. R. A. Prado authored
These devicetrees override a rt5682 node to use the rt5682s compatible, however, unlike rt5682, rt5682s doesn't have a VBAT supply. Remove the inexistent supply in the rt5682s nodes. Signed-off-by:
Nícolas F. R. A. Prado <nfraprado@collabora.com> Signed-off-by:
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Nícolas F. R. A. Prado authored
The DBVDD and LDO1-IN supplies for rt5682 are required but are missing. They are supplied by the same power rail as AVDD. Add them. Reviewed-by:
AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Signed-off-by:
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Bjorn Andersson authored
The first PM8540 PMIC has an available RTC block, describe this in the SA8295P ADP. Mark it as wakeup-source to allow waking the system from sleep. Signed-off-by:
Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by:
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- 02 Dec, 2022 3 commits
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Johan Hovold authored
There are three UFS reference clocks on SC8280XP which are used as follows: - The GCC_UFS_REF_CLKREF_CLK clock is fed to any UFS device connected to either controller. - The GCC_UFS_1_CARD_CLKREF_CLK and GCC_UFS_CARD_CLKREF_CLK clocks provide reference clocks to the two PHYs. Note that this depends on first updating the clock driver to reflect that all three clocks are sourced from CXO. Specifically, the UFS controller driver expects the device reference clock to have a valid frequency: ufshcd-qcom 1d84000.ufs: invalid ref_clk setting = 0 Fixes: 152d1faf ("arm64: dts: qcom: add SC8280XP platform") Fixes: 8d6b458c ("arm64: dts: qcom: sc8280xp: fix ufs_card_phy ref clock") Fixes: f3aa975e ("arm64: dts: qcom: sc8280xp: correct ref clock for ufs_mem_phy") Link: https://lore.kernel.org/lkml/Y2OEjNAPXg5BfOxH@hovoldconsulting.com/ Cc: stable@vger.kernel.org # 5.20 Signed-off-by:
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Johan Hovold authored
The devices on the SC8280XP PCIe buses are cache coherent and must be marked as such to avoid data corruption. A coherent device can, for example, end up snooping stale data from the caches instead of using data written by the CPU through the non-cacheable mapping which is used for consistent DMA buffers for non-coherent devices. Note that this is much more likely to happen since commit c44094ee ("arm64: dma: Drop cache invalidation from arch_dma_prep_coherent()") that was added in 6.1 and which removed the cache invalidation when setting up the non-cacheable mapping. Marking the PCIe devices as coherent specifically fixes the intermittent NVMe probe failures observed on the Thinkpad X13s, which was due to corruption of the submission and completion queues. This was typically observed as corruption of the admin submission queue (with well-formed completion): could not locate request for tag 0x0 nvme nvme0: invalid id 0 completed on queue 0 or corruption of the admin or I/O completion queues (malformed completion): could not locate request for tag 0x45f nvme nvme0: invalid id 25695 completed on queue 25965 presumably as these queues are small enough to not be allocated using CMA which in turn make them more likely to be cached (e.g. due to accesses to nearby pages through the cacheable linear map). Increasing the buffer sizes to two pages to force CMA allocation also appears to make the problem go away. Fixes: 813e8315 ("arm64: dts: qcom: sc8280xp/sa8540p: add PCIe2-4 nodes") Signed-off-by:
Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Reviewed-by:
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Bjorn Andersson authored
Mergeback arm64-fixes-for-6.1 to avoid merge conflicts.
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- 15 Nov, 2022 7 commits
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Konrad Dybcio authored
The DMA properties in this DT are identical to the ones already defined in sdm845.dtsi. Remove them. Signed-off-by:
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Konrad Dybcio authored
Wire up necessary supplies to USB PHYs to enable USB3 on Sagami and remove all the limit-to-USB2 properties. Signed-off-by:
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Konrad Dybcio authored
Configure most RPMh-controlled regulators on SoMC Sagami. The missing ones (on pm8350b and pm8008[ij]) will be configured when driver support is added. Thankfully, it looks like PDX215 and PDX214 don't have any differences when it comes to PM8350/PM8350C/PMR735a. Signed-off-by:
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Douglas Anderson authored
The 1-mic and 3-mic dtsi still had two minor cosmetic differences after commit '3d11e7e1 ("arm64: dts: qcom: sc7280: sort out the "Status" to last property with sc7280-herobrine-audio-rt5682.dtsi")'. Let's fix them so the two files diff better. This is expected to have no effect though it will slightly change the generated dtb by removing an unnecessary 'status = "okay"' from the sound node. Signed-off-by:
Douglas Anderson <dianders@chromium.org> Reviewed-by:
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Krzysztof Kozlowski authored
Hex numbers in addresses and sizes should be rather eight digits, not nine. Drop leading zeros. No functional change (same DTB). Suggested-by:
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Krzysztof Kozlowski authored
PCIe on MSM8996 and MSM8998 use the same clocks, so use one order to make the binding simpler. Signed-off-by:
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Krzysztof Kozlowski authored
Add new compatible for MSM8998 (compatible with MSM8996) to allow further customizing if needed and to accurately describe the hardware. Signed-off-by:
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- 12 Nov, 2022 10 commits
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Johan Hovold authored
Enable the Qualcomm QCNFA765 Wireless Network Adapter connected to PCIe4. Signed-off-by:
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Johan Hovold authored
Enable the modem connected to the PCIe3a M.2 connector. Signed-off-by:
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Johan Hovold authored
Enable the NVMe SSD connected to PCIe2. Signed-off-by:
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Johan Hovold authored
Enable the Qualcomm QCNFA765 Wireless Network Adapter connected to PCIe4. Signed-off-by:
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Johan Hovold authored
Enable the SDX55 modem connected to PCIe3. Signed-off-by:
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Johan Hovold authored
Enable the NVMe SSD connected to PCIe2. Signed-off-by:
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Johan Hovold authored
Rename the backlight and misc regulators according to the net names. Signed-off-by:
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Johan Hovold authored
The SA8295P-ADP has up to four PCIe interfaces implemented by three or four controllers: PCIe2A, PCIe3A/PCIe3B and PCIe4. PCIe2 is used in x4 mode, while PCIe3 can be used in either x2 or x4 mode. Enable both PCIe3A and PCI3B in x2 mode for now. Signed-off-by:
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Johan Hovold authored
The SC8280XP platform has seven PCIe controllers: PCIe0 USB4 PCIe1 USB4 PCIe2A 4-lane PCIe2B 2-lane PCIe3A 4-lane PCIe3B 2-lane PCIe4 1-lane while SA8540P only has five (PCIe2-4). Add devicetree nodes for the PCIe2-4 controllers and their PHYs. Signed-off-by:
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Richard Acayan authored
The Qualcomm Snapdragon 670 has been out for a while. Add a device tree for it and the Google Pixel 3a as the first device. The Pixel 3a has the same bootloader issue as the Pixel 3 and will not work on Android 10 bootloaders or later until it gets fixed for the Pixel 3. SoC Initial Features: - power management - clocks - pinctrl - eMMC - USB 2.0 - GENI I2C - IOMMU - RPMh - interrupts Device-Specific Initial Features: - side buttons (keys) - regulators - touchscreen Signed-off-by:
Richard Acayan <mailingradian@gmail.com> Signed-off-by:
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- 11 Nov, 2022 4 commits
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Sibi Sankar authored
The Google Herobrine WIFI SKU can save 256M by not having modem/mba/rmtfs memory regions defined. Add the dts fragment and mark all the board files appropriately. Reviewed-by:
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Sibi Sankar authored
When the modem node was re-located to a separate LTE source file "sc7280-herobrine-lte-sku.dtsi", some of the previous LTE users weren't marked appropriately. Fix this by marking all Qualcomm reference devices as LTE. Suggested-by:
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Luca Weiss authored
Fairphone 4 uses sdhc_2 for the SD card, configure the pins for it and enable it. The regulators which are exclusively used for SDHCI have their maximum voltage decreased to what downstream sets on the consumer side, like on many other platforms and allowed to set the load. Signed-off-by:
Luca Weiss <luca.weiss@fairphone.com> Reviewed-by:
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Krzysztof Kozlowski authored
spi-max-frequency is a property of SPI device, not the controller: qcom/sm8450-hdk.dtb: geniqup@8c0000: spi@880000: Unevaluated properties are not allowed ('spi-max-frequency' was unexpected Signed-off-by:
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- 10 Nov, 2022 7 commits
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Bjorn Andersson authored
Add gpio-keys for exposing the LID switch state. Signed-off-by:
Bjorn Andersson <bjorn.andersson@linaro.org> Reviewed-by:
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Krzysztof Kozlowski authored
DT schema expects TLMM pin configuration nodes to be named with '-state' suffix and their optional children with '-pins' suffix. Signed-off-by:
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Srinivasa Rao Mandadapu authored
Remove redundant and undocumented property qcom,port-offset in soundwire controller nodes. This patch is required to avoid dtbs_check errors with qcom,soundwire.yaml Fixes: 12ef689f ("arm64: dts: qcom: sc7280: Add nodes for soundwire and va tx rx digital macro codecs") Signed-off-by:
Srinivasa Rao Mandadapu <quic_srivasam@quicinc.com> Co-developed-by:
Ratna Deepthi Kudaravalli <quic_rkudarav@quicinc.com> Signed-off-by:
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Srinivasa Rao Mandadapu authored
Remove redundant and undocumented property qcom,port-offset in soundwire controller nodes. This patch is required to avoid dtbs_check errors with qcom,soundwire.yaml Fixes: 24f52ef0 ("arm64: dts: qcom: sm8250: Add nodes for tx and rx macros with soundwire masters") Signed-off-by:
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Srinivasa Rao Mandadapu authored
Update soundwire secondary nodes of WSA speaker to match with dt-bindings pattern properties regular expression. This modification is required to avoid dtbs-check errors occurred with qcom,soundwire.yaml. Signed-off-by:
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Alex Elder authored
In "sc7280-idp.dts", the IPA node is modified after being defined. However that file includes "sc7280-idp.dtsi", which also modifies the IPA node (in the same way). This only needs to be done in "sc7280-idp.dtsi". Signed-off-by:
Alex Elder <elder@linaro.org> Reviewed-by:
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Maulik Shah authored
Add power-domains property which allows apps_rsc device to attach to cluster power domain on sm8150, sm8250, sm8350 and sm8450. Signed-off-by:
Maulik Shah <quic_mkshah@quicinc.com> Reviewed-by:
Ulf Hansson <ulf.hansson@linaro.org> Tested-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> # SM8450 Signed-off-by:
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