- 21 Mar, 2023 19 commits
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Sasha Neftin authored
DMA coalescing is not applicable for i225 parts. This patch comes to tidy up the driver code. Signed-off-by:
Sasha Neftin <sasha.neftin@intel.com> Tested-by:
Naama Meir <naamax.meir@linux.intel.com> Signed-off-by:
Tony Nguyen <anthony.l.nguyen@intel.com>
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Dawid Wesierski authored
There was a problem with resuming ping after conducting a PCI reset. This commit adds two functions, igbvf_io_prepare and igbvf_io_done, which, after being added to the pci_error_handlers struct, will prepare the drivers for a PCI reset and then bring the interface up and reset it after. This will prevent the driver from ending up in incorrect state. Test_and_set_bit is highly reliable in this context, so we are not including a timeout in this commit This introduces 900ms - 1100ms of overhead to this operation but it's in non-time-critical flow. And also allows the driver to continue functioning after the reset. Functionality documented in ethernet-controller-i350-datasheet 4.2.1.3 https://www.intel.com/content/www/us/en/products/details/ethernet/gigabit-controllers/i350-controllers/docs.htmlSigned-off-by:
Dawid Wesierski <dawidx.wesierski@intel.com> Signed-off-by:
Kamil Maziarz <kamil.maziarz@intel.com> Reviewed-by:
Michal Kubiak <michal.kubiak@intel.com> Tested-by:
Marek Szlosek <marek.szlosek@intel.com> Signed-off-by:
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Andrii Staikov authored
Driver's .adjfine interface functions use adjust_by_scaled_ppm and diff_by_scaled_ppm introduced in commit 1060707e ("ptp: introduce helpers to adjust by scaled parts per million") to calculate the required adjustment in a concise manner, but not igb_ptp_adjfine_82580. Fix it by introducing IGB_82580_BASE_PERIOD and changing function logic to use diff_by_scaled_ppm. Signed-off-by:
Andrii Staikov <andrii.staikov@intel.com> Reviewed-by:
Jacob Keller <jacob.e.keller@intel.com> Tested-by: Pucha Himasekhar Reddy <himasekharx.reddy.pucha@intel.com> (A Contingent worker at Intel) Signed-off-by:
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Nathan Chancellor authored
With clang's kernel control flow integrity (kCFI, CONFIG_CFI_CLANG), indirect call targets are validated against the expected function pointer prototype to make sure the call target is valid to help mitigate ROP attacks. If they are not identical, there is a failure at run time, which manifests as either a kernel panic or thread getting killed. A warning in clang aims to catch these at compile time, which reveals: drivers/net/ethernet/pasemi/pasemi_mac.c:1665:21: error: incompatible function pointer types initializing 'netdev_tx_t (*)(struct sk_buff *, struct net_device *)' (aka 'enum netdev_tx (*)(struct sk_buff *, struct net_device *)') with an expression of type 'int (struct sk_buff *, struct net_device *)' [-Werror,-Wincompatible-function-pointer-types-strict] .ndo_start_xmit = pasemi_mac_start_tx, ^~~~~~~~~~~~~~~~~~~ 1 error generated. ->ndo_start_xmit() in 'struct net_device_ops' expects a return type of 'netdev_tx_t', not 'int'. Adjust the return type of pasemi_mac_start_tx() to match the prototype's to resolve the warning. While PowerPC does not currently implement support for kCFI, it could in the future, which means this warning becomes a fatal CFI failure at run time. Link: https://github.com/ClangBuiltLinux/linux/issues/1750Signed-off-by:Nathan Chancellor <nathan@kernel.org> Reviewed-by:
Horatiu Vultur <horatiu.vultur@microchip.com> Link: https://lore.kernel.org/r/20230319-pasemi-incompatible-pointer-types-strict-v1-1-1b9459d8aef0@kernel.orgSigned-off-by:
Paolo Abeni <pabeni@redhat.com>
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Josef Miegl authored
The Geneve encapsulation, as defined in RFC 8926, has a Protocol Type field, which states the Ethertype of the payload appearing after the Geneve header. Commit 435fe1c0 ("net: geneve: support IPv4/IPv6 as inner protocol") introduced a new IFLA_GENEVE_INNER_PROTO_INHERIT flag that allowed the use of other Ethertypes than Ethernet. However, it did not get rid of a restriction that prohibits receiving payloads other than Ethernet, instead the commit white-listed additional Ethertypes, IPv4 and IPv6. This patch removes this restriction, making it possible to receive any Ethertype as a payload, if the IFLA_GENEVE_INNER_PROTO_INHERIT flag is set. The restriction was set in place back in commit 0b5e8b8e ("net: Add Geneve tunneling protocol driver"), which implemented a protocol layer driver for Geneve to be used with Open vSwitch. The relevant discussion about introducing the Ethertype white-list can be found here: https://lore.kernel.org/netdev/CAEP_g=_1q3ACX5NTHxLDnysL+dTMUVzdLpgw1apLKEdDSWPztw@mail.gmail.com/ <quote> >> + if (unlikely(geneveh->proto_type != htons(ETH_P_TEB))) > > Why? I thought the point of geneve carrying protocol field was to > allow protocols other than Ethernet... is this temporary maybe? Yes, it is temporary. Currently OVS only handles Ethernet packets but this restriction can be lifted once we have a consumer that is capable of handling other protocols. </quote> This white-list was then ported to a generic Geneve netdevice in commit 371bd106 ("geneve: Consolidate Geneve functionality in single module."). Preserving the Ethertype white-list at this point made sense, as the Geneve device could send out only Ethernet payloads anyways. However, now that the Geneve netdevice supports encapsulating other payloads with IFLA_GENEVE_INNER_PROTO_INHERIT and we have a consumer capable of other protocols, it seems appropriate to lift the restriction and allow any Geneve payload to be received. Signed-off-by:
Josef Miegl <josef@miegl.cz> Reviewed-by:
Simon Horman <simon.horman@corigine.com> Reviewed-by:
Eyal Birger <eyal.birger@gmail.com> Link: https://lore.kernel.org/r/20230319220954.21834-1-josef@miegl.czSigned-off-by:
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Álvaro Fernández Rojas authored
BCM63xx RGMII ports require additional configuration in order to work. Signed-off-by:
Álvaro Fernández Rojas <noltari@gmail.com> Reviewed-by:
Andrew Lunn <andrew@lunn.ch> Link: https://lore.kernel.org/r/20230319220805.124024-1-noltari@gmail.comSigned-off-by:
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Russell King (Oracle) authored
pcs_get_state() implementations are not supposed to alter an_enabled. Remove this assignment. Fixes: b3591c2a ("net: dsa: qca8k: Switch to PHYLINK instead of PHYLIB") Signed-off-by:
Russell King (Oracle) <rmk+kernel@armlinux.org.uk> Link: https://lore.kernel.org/r/E1pdsE5-00Dl2l-8F@rmk-PC.armlinux.org.ukSigned-off-by:
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Marek Behún authored
Commit 2c7e46ed ("net: dsa: mv88e6xxx: mask apparently non-existing phys during probing") added non-trivial bus->phy_mask in mv88e6xxx_mdio_register() in order to avoid excessive mdio bus transactions during probing. But the mask is incorrect for switches with non-zero phy_base_addr (such as 88E6341). Fix this. Fixes: 2c7e46ed ("net: dsa: mv88e6xxx: mask apparently non-existing phys during probing") Signed-off-by:
Marek Behún <kabel@kernel.org> Tested-by:
Klaus Kudielka <klaus.kudielka@gmail.com> Reviewed-by:
Vladimir Oltean <olteanv@gmail.com> Link: https://lore.kernel.org/r/20230319140238.9470-1-kabel@kernel.orgSigned-off-by:
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Tom Rix authored
clang with W=1 reports drivers/net/ethernet/chelsio/cxgb3/sge.c:169:32: error: unused function 'fl_to_qset' [-Werror,-Wunused-function] static inline struct sge_qset *fl_to_qset(const struct sge_fl *q, int qidx) ^ This function is not used, so remove it. Signed-off-by:Tom Rix <trix@redhat.com> Reviewed-by:
Jakub Kicinski <kuba@kernel.org>
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Jakub Kicinski authored
Daniel Golle says: ==================== net: ethernet: mtk_eth_soc: various enhancements This series brings a variety of fixes and enhancements for mtk_eth_soc, adds support for the MT7981 SoC and facilitates sharing the SGMII PCS code between mtk_eth_soc and mt7530. The whole series has been tested on MT7622+MT7531 (BPi-R64), MT7623+MT7530 (BPi-R2), MT7981+GPY211 (GL.iNet GL-MT3000) and MT7986+MT7531 (BPi-R3). On the BananaPi R3 a variete of SFP modules have been tested, all of them (some SGMII with PHY, others 2500Base-X or 1000Base-X without PHY) are working well now, however, some of them need manually disabling of autonegotiation for the link to come up. ==================== Link: https://lore.kernel.org/r/cover.1679230025.git.daniel@makrotopia.orgSigned-off-by:
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Daniel Golle authored
Implement regmap access wrappers, for now only to be used by the pcs-mtk-lynxi driver. Make use of this external PCS driver and drop the now reduntant implementation in mt7530.c. As a nice side effect the SGMII registers can now also more easily be inspected for debugging via /sys/kernel/debug/regmap. Tested-by:
Bjørn Mork <bjorn@mork.no> Signed-off-by:
Daniel Golle <daniel@makrotopia.org> Tested-by:
Frank Wunderlich <frank-w@public-files.de> Reviewed-by:
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Daniel Golle authored
Now that we got a PCS driver, use it and remove the now redundant PCS code and it's header macros from the Ethernet driver. Signed-off-by:
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Daniel Golle authored
The SGMII core found in several MediaTek SoCs is identical to what can also be found in MediaTek's MT7531 Ethernet switch IC. As this has not always been clear, both drivers developed different implementations to deal with the PCS. Recently Alexander Couzens pointed out this fact which lead to the development of this shared driver. Add a dedicated driver, mostly by copying the code now found in the Ethernet driver. The now redundant code will be removed by a follow-up commit. Suggested-by:
Alexander Couzens <lynxis@fe80.eu> Suggested-by:
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Daniel Golle authored
The PPE units found in MT7622 and newer support packet and byte accounting of hw-offloaded flows. Add support for reading those counters as found in MediaTek's SDK[1]. [1]: https://git01.mediatek.com/plugins/gitiles/openwrt/feeds/mtk-openwrt-feeds/+/bc6a6a375c800dc2b80e1a325a2c732d1737df92Tested-by:
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Daniel Golle authored
Set MDIO bus clock frequency and allow setting a custom maximum frequency from device tree. Reviewed-by:
Florian Fainelli <f.fainelli@gmail.com> Tested-by:
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Daniel Golle authored
Add mediatek,pnswap boolean property needed on many boards using the MediaTek MT7981 SoC. Reviewed-by:
Rob Herring <robh@kernel.org> Signed-off-by:
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Daniel Golle authored
Convert mediatek,sgmiiisys bindings to DT schema format. Add maintainer Matthias Brugger, no maintainers were listed in the original documentation. As this node is also referenced by the Ethernet controller and used as SGMII PCS add this fact to the description. Move the file to Documentation/devicetree/bindings/net/pcs/ which seems more appropriate given that the great majority of registers are related to SGMII PCS functionality and only one register represents clock bits. Reviewed-by:
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Daniel Golle authored
Introduce DT bindings for the MT7981 SoC to mediatek,net.yaml. Reviewed-by:
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Daniel Golle authored
The MediaTek MT7981 SoC comes with two 1G/2.5G SGMII ports, just like MT7986. In addition MT7981 is equipped with a built-in 1000Base-T PHY which can be used with GMAC1. As many MT7981 boards make use of inverting SGMII signal polarity, add new device-tree attribute 'mediatek,pn_swap' to support them. Signed-off-by:
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- 20 Mar, 2023 15 commits
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Lukas Bulwahn authored
Commit 053fdaa8 ("nfc: mrvl: Move platform_data struct into driver") moves the nfcmrvl.h header file from include/linux/platform_data to the driver's directory, but misses to adjust MAINTAINERS. Hence, ./scripts/get_maintainer.pl --self-test=patterns complains about a broken reference. Just remove the file entry in NFC SUBSYSTEM, as the new location of the code is already covered by another pattern in that section. Fixes: 053fdaa8 ("nfc: mrvl: Move platform_data struct into driver") Signed-off-by:
Lukas Bulwahn <lukas.bulwahn@gmail.com> Reviewed-by:
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by:
David S. Miller <davem@davemloft.net>
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Heiner Kallweit authored
Now that rtl_hw_aspm_clkreq_enable() is a no-op for chip versions < 32, we can consolidate disabling ASPM before EPHY access in rtl_hw_start(). Signed-off-by:
Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by:
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David S. Miller authored
Heiner Kallweit says: ==================== net: phy: reuse SMSC PHY driver functionality in the meson-gxl PHY driver The Amlogic Meson internal PHY's have the same register layout as certain SMSC PHY's (also for non-c22-standard registers). This seems to be more than just coincidence. Apparently they also need the same workaround for EDPD mode (energy detect power down). Therefore let's reuse SMSC PHY driver functionality in the meson-gxl PHY driver. ==================== Signed-off-by: -
Heiner Kallweit authored
The Amlogic Meson internal PHY's have the same register layout as certain SMSC PHY's (also for non-c22-standard registers). This seems to be more than just coincidence. Apparently they also need the same workaround for EDPD mode (energy detect power down). Therefore let's reuse SMSC PHY driver functionality in the meson-gxl PHY driver. Tested with a G12A internal PHY. I don't have GXL test hw, therefore I replace only the callbacks that are identical in the SMSC PHY driver. Signed-off-by:
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Heiner Kallweit authored
The Amlogic Meson internal PHY's have the same register layout as certain SMSC PHY's (also for non-c22-standard registers). This seems to be more than just coincidence. Apparently they also need the same workaround for EDPD mode (energy detect power down). Therefore let's export SMSC PHY driver functionality for use by the meson-gxl PHY driver. Signed-off-by:
Chris Healy <healych@amazon.com> Signed-off-by:
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David S. Miller authored
Colin Foster says: ==================== add support for ocelot external ports This is the start of part 3 of what is hopefully a 3-part series to add Ethernet switching support to Ocelot chips. Part 1 of the series (A New Chip) added general support for Ocelot chips that were controlled externally via SPI. https://lore.kernel.org/all/20220815005553.1450359-1-colin.foster@in-advantage.com/ Part 2 of the series (The Ethernet Strikes Back) added DSA Ethernet support for ports 0-3, which are the four copper ports that are internal to the chip. https://lore.kernel.org/all/20230127193559.1001051-1-colin.foster@in-advantage.com/ Part 3 will, at a minimum, add support for ports 4-7, which are configured to use QSGMII to an external phy (Return Of The QSGMII). With any luck, and some guidance, support for SGMII, SFPs, etc. will also be part of this series. V1 was submitted as an RFC - and that was rightly so. I suspected I wasn't doing something right, and that was certainly the case. V2 is much cleaner, so hopefully upgrading it to PATCH status is welcomed. Thanks to Russell and Vladimir for correcting my course from V1. In V1 I included a device tree snippet. I won't repeat that here, but I will include a boot log snippet, in case it is of use: ==================== Signed-off-by:
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Colin Foster authored
The VSC7512 has four ports with internal phys that are already supported. There are additional ports that can be configured to work with external phys. Add support for these additional ethernet ports. Signed-off-by:
Colin Foster <colin.foster@in-advantage.com> Signed-off-by:
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Colin Foster authored
Ports for Ocelot devices (VSC7511, VSC7512, VSC7513 and VSC7514) support external phys. When external phys are used, additional configuration on each port is required to enable QSGMII mode and set external phy modes. Add a configurable hook into these routines, so the external ports can be used. Signed-off-by:
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Colin Foster authored
If a user of the Felix driver has a port running in SGMII / QSGMII mode, it will need to utilize phylink_mac_config(). Add this configurability. Signed-off-by:
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Colin Foster authored
The VSC7512 and VSC7514 have internal PLLs that can be used to control different peripherals. Initialize these high speed I/O (HSIO) PLLs when they exist, so that dependent peripherals like QSGMII can function. Signed-off-by:
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Colin Foster authored
During chip initialization, ports that use SGMII / QSGMII to interface to external phys need to be configured on the VSC7513 and VSC7514. Expose this configuration routine, so it can be used by DSA drivers. Signed-off-by:
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Colin Foster authored
The ocelot-switch driver can utilize the phylink_mac_config routine. Move this to the ocelot library location and export the symbol to make this possible. Signed-off-by:
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Colin Foster authored
Ocelot chips have an internal PLL that must be used when communicating through external phys. Expose the init routine, so it can be used by other drivers. Signed-off-by:
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Colin Foster authored
Add support for the Ocelot SERDES module to support functionality of all non-internal phy ports. Signed-off-by:
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Colin Foster authored
The phy-ocelot-serdes module has exclusively been used in a syscon setup, from an internal CPU. The addition of external control of ocelot switches via an existing MFD implementation means that syscon is no longer the only interface that phy-ocelot-serdes will see. In the MFD configuration, an IORESOURCE_REG resource will exist for the device. Utilize this resource to be able to function in both syscon and non-syscon configurations. Signed-off-by:
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- 19 Mar, 2023 6 commits
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David S. Miller authored
Horatiu Vultur says: ==================== net: lan966x: Improve TX/RX of frames from/to CPU The first patch of this series improves the RX side. As it seems to be an expensive operation to read the RX timestamp for every frame, then read it only if it is required. This will give an improvement of ~70mbit on the RX side. The second patch stops using the packing library. This improves mostly the TX side as this library is used to set diffent bits in the IFH. If this library is replaced with a more simple/shorter implementation, this gives an improvement of more than 100mbit on TX side. All the measurements were done using iperf3. v1->v2: - update lan966x_ifh_set to set the bytes and not each bit individually ==================== Signed-off-by: -
Horatiu Vultur authored
When a frame is injected from CPU, it is required to create an IFH(Inter frame header) which sits in front of the frame that is transmitted. This IFH, contains different fields like destination port, to bypass the analyzer, priotity, etc. Lan966x it is using packing library to set and get the fields of this IFH. But this seems to be an expensive operations. If this is changed with a simpler implementation, the RX will be improved with ~5Mbit while on the TX is a much bigger improvement as it is required to set more fields. Below are the numbers for TX. Before: [ 5] 0.00-10.02 sec 439 MBytes 367 Mbits/sec 0 sender After: [ 5] 0.00-10.00 sec 578 MBytes 485 Mbits/sec 0 sender Signed-off-by:
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Horatiu Vultur authored
Whenever a frame was received to the CPU, the HW is timestamping the frame. In the IFH(Inter Frame Header) it is found the nanosecond part of the timestamps the SW is required to read from HW the second part. But reading the second part it seems to be a expensive operations, so so change this such to read the second part only when rx filter is enabled. Doing this change gives the RX a performance boost of ~70mbit. before: [ 5] 0.00-10.01 sec 546 MBytes 457 Mbits/sec 0 sender now: [ 5] 0.00-10.01 sec 652 MBytes 530 Mbits/sec 0 sender Signed-off-by:
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Eric Dumazet authored
Use PACKET_SOCK_QDISC_BYPASS atomic bit instead of a pointer. This removes one indirect call in fast path, and READ_ONCE()/WRITE_ONCE() annotations as well. Signed-off-by:
Eric Dumazet <edumazet@google.com> Suggested-by:
Willem de Bruijn <willemb@google.com> Cc: Daniel Borkmann <daniel@iogearbox.net> Reviewed-by:
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Harini Katakam authored
Reset TX when halt times out i.e. disable TX, clean up TX BDs, interrupts (already done) and enable TX. This addresses the issue observed when iperf is run at 10Mps Half duplex where, after multiple collisions and retries, TX halts. Signed-off-by:
Harini Katakam <harini.katakam@xilinx.com> Signed-off-by:
Michal Simek <michal.simek@xilinx.com> Signed-off-by:
Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com> Reviewed-by:
Michal Swiatkowski <michal.swiatkowski@linux.intel.com> Acked-by:
Nicolas Ferre <nicolas.ferre@microchip.com> Signed-off-by:
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Tony Nguyen authored
There are likely no users of this driver as the hardware has been discontinued since 2010. Remove the driver and all references to it in documentation. Suggested-by:
Jesse Brandeburg <jesse.brandeburg@intel.com> Signed-off-by:
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