- 10 May, 2013 23 commits
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Imre Deak authored
is_pch_edp() will be removed by the next patch, so replace it by a check for the port and device type. Signed-off-by:
Imre Deak <imre.deak@intel.com> Signed-off-by:
Daniel Vetter <daniel.vetter@ffwll.ch>
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Imre Deak authored
is_pch_edp() will be removed in a follow-up patch, so replace it with a check for the port and VBT info (for port-D eDP). Also make things a bit clearer by using a switch on the ports. v2: - make the comment about not setting the conder type for DP clearer (Ville) Signed-off-by:
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Imre Deak authored
On ILK-IVB the CPU side eDP is always on port-A. Also reduce somewhat the debug verbosity. v2: - reduce debug verbosity Signed-off-by:
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Imre Deak authored
On HSW the CPU side eDP is always on port-A, the PCH side eDP is always on port-D. Signed-off-by:
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Imre Deak authored
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Jesse Barnes authored
Works pretty well actually. Signed-off-by:
Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by:
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Jesse Barnes authored
In some cases, we may not need GTT address space allocated to a stolen object, so allow passing -1 to the preallocated function to indicate as much. v2: remove BUG_ON(gtt_offset & 4095) now that -1 is allowed (Ville) Reviewed-by:
Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by:
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Jesse Barnes authored
But we need to get the right stolen base and make pre-allocated objects for BIOS stuff so we don't clobber it. If the BIOS hasn't allocated a power context, we allocate one here too, from stolen space as required by the docs. v2: fix stolen to phys if ladder (Ben) keep BIOS reserved space out of allocator altogether (Ben) v3: fix mask of stolen base (Ben) v4: clean up preallocated object on unload (Ben) don't zero reg on unload (Jesse) fix mask harder (Jesse) v5: use unref for freeing stolen bits (Chris) move alloc/free to intel_pm.c (Chris) v6: NULL pctx at disable time so error paths work (Ben) v7: use correct PCI device for config read (Jesse) Reviewed-by:Ben Widawsky <benjamin.widawsky@intel.com> Signed-off-by:
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Ville Syrjälä authored
If the calculated FBC watermark is no good, we simply disable FBC watermarks. But we fail to re-enable them later if the calculated watermark becomes good again. Fix that, but remember to leave FBC watermarks disabled on ILK since that's required by some workarounds. v2: Fix checkpatch complaint Signed-off-by:
Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by:
Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by:
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Imre Deak authored
For the device to enter D3 we should enable PCH clock gating. v2: - use HAS_PCH_LPT instead of IS_HASWELL (Ville, Paolo) - rename lpt_allow_clock_gating to lpt_suspend_hw (Paolo) Signed-off-by:
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Jani Nikula authored
commit 142e2398 Author: Egbert Eich <eich@suse.de> Date: Thu Apr 11 15:57:57 2013 +0200 drm/i915: Add bit field to record which pins have received HPD events (v3) added a bit field for hotplug event tracking. There ended up being three different v3 of the patch: [1], [2], and [3]. Apparently [1] was the correct one, but some frankenstein combination of the three got committed, which reversed the logic for setting the hotplug bits and misplaced a continue statement, skipping the hotplug irq storm handling altogether. This lead to broken hotplug detection, bisected to commit 321a1b30 Author: Egbert Eich <eich@suse.de> Date: Thu Apr 11 16:00:26 2013 +0200 drm/i915: Only reprobe display on encoder which has received an HPD event (v2) which uses the incorrectly set hotplug event bits. Fix the mess. [1] http://mid.gmane.org/1366112220-7638-6-git-send-email-eich@suse.de [2] http://mid.gmane.org/1365688677-13682-1-git-send-email-eich@suse.de [3] http://mid.gmane.org/1365688996-13874-1-git-send-email-eich@suse.deSigned-off-by:
Jani Nikula <jani.nikula@intel.com> Signed-off-by:
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Damien Lespiau authored
We did not mention the workaround name when implementing those. This should help us track what we already implement. Signed-off-by:
Damien Lespiau <damien.lespiau@intel.com> Reviewed-by:
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Damien Lespiau authored
Signed-off-by:
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Paulo Zanoni authored
We already have the same check on intel_enable_ddi. This patch prevents "unclaimed register" messages when the power well is disabled. V2: Reset intel_crtc->eld_vld to false after the mode_set function. V3: Add both "type != INTEL_OUTPUT_EDP" requested. Signed-off-by:
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Paulo Zanoni authored
This fixes "unclaimed register" messages when the power well is disabled and there's a GPU hang. v2: Use the new intel_display_power_enabled(). v3: Use the new domains for intel_display_power_enabled(). Signed-off-by:
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Paulo Zanoni authored
In the error state function we read the registers without checking if the power well is on, so after doing this we have to clear the FPGA_DBG_RM_NOCLAIM bit to prevent the next I915_WRITE from detecting it and printing an error message. The first version of this patch was checking for the power well state and then avoiding reading registers that were off, but the reviewers requested to just read the registers any way and then later clear the FPGA_DBG_RM_NOCLAIM bit. Signed-off-by:
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Paulo Zanoni authored
We need to dump these registers if we want to properly interpret the others. Signed-off-by:
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Paulo Zanoni authored
This should replace intel_using_power_well. The idea is that we're adding the requested power domain as an argument, so this might enable the code to look less platform-specific and also allows us to easily add new domains in case we need. v2: Add more domains to enum intel_display_power_domain v3: Even more domains requested Requested-by:
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Jesse Barnes authored
Supposedly we should use the DAC divider for <300MHz pixel clocks, but as that doesn't actually work as well as the high freq divider here in practice, just use the high freq divider all the time. v2: remove unconditional write (Jesse) check for pixel rate properly (Jesse) v3: give up, the DAC divider apparently doesn't work, and low res modes work ok (Jesse) remove debug msg (Jesse) Signed-off-by:Kenneth Graunke <kenneth@whitecape.org> Signed-off-by:
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Jesse Barnes authored
This regression was introduced in: commit b074cec8 Author: Jesse Barnes <jbarnes@virtuousgeek.org> Date: Thu Apr 25 12:55:02 2013 -0700 drm/i915: move PCH pfit controls into pipe_config In refactoring this, it was only applied to eDP, which is incorrect. In fact, if we ever use the panel fitter to deal with overscan on HDMI, we'll need to extend it again, so just drop the conditional altogether. v2: drop check for eDP since we can use the fitter in any config (Daniel) Signed-off-by:
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Jesse Barnes authored
Both the docs and the existing code were wrong. So fix both and use a switch statement like we do elsewhere to make things simple & clear. Signed-off-by:
Ben Widawsky <ben@bwidawsk.net> Signed-off-by:
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Jesse Barnes authored
Instead of returning the cached value, which is just what the kernel requested. Reviewed-by:
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Jan-Simon Möller authored
Description: intel_gmbus_is_forced_bit is no extern as its body is right below. Likewise for intel_gmbus_is_port_valid. This fixes a compilation issue with clang. An initial version of this patch was developed by PaX Team <pageexec at freemail.hu>. This is respin of this patch. 20130509: v2: (re-)add inline upon request. Signed-off-by:
Jan-Simon Möller <dl9pf@gmx.de> CC: pageexec@freemail.hu CC: daniel.vetter@ffwll.ch CC: airlied@linux.ie CC: intel-gfx@lists.freedesktop.org CC: dri-devel@lists.freedesktop.org CC: linux-kernel@vger.kernel.org [danvet: Bikeshed commit message.] Signed-off-by:
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- 06 May, 2013 12 commits
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Ben Widawsky authored
It also makes some sense IMO to have these two functions separate irrespective of the number of callers. Only the single caller for now, but that will change as we add more PPGTTs. Signed-off-by:
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Ben Widawsky authored
Because PPGTT PDEs within the GTT are calculated in cachelines (HW guys consistency ftw) we do a divide which will wreak havoc if this is wrong, and I know that from experience). If/when we move to multiple PPGTTs this will have to become a WARN, and return an error. For now however it should always be considered fatal, and only a developer could hit it. Signed-off-by:
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Ben Widawsky authored
Because our context refcounting doesn't grab a ref at lookup time, it is unsafe to do so without the lock. NOTE: We don't have an easy way to put the assertion in the lookup function which is where this really belongs. Context switching is good enough because it actually asserts even more correctness by protecting the default_context. Signed-off-by:
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Daniel Vetter authored
Only one caller. Also drop the intel_ prefix as is now customary for platform specific and static functions. Reviewed-by:
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Daniel Vetter authored
- PCH_ prefix for pch registers on ibx/cpt/ppt. - Drop the DP_ from the link defines, redundant. - Drop the GMCH from the data defines and instead give the special g4x registers a consistent _G4X postfix. v2: - Realign #defines and use tabs (Paulo). Reviewed-by:
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Daniel Vetter authored
This is possible thanks to moving the m/n stuff into pipe_config. Unfortunately we need to move them a bit to avoid forward declarations. Reviewed-by:
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Daniel Vetter authored
While at it, also extract a common helper to copy the timings from the cpu transcoder to the pch transcoder. That way it's really explicit how the lpt transcoder is hardcoded. v2: - Re-align #defines properly (Paulo). - Use cpu_transcoder when copying pipe timings (Paulo). - s/intel_pch_transcoder_enable/intel_pch_transcoder_set_timings/ since we already have a pch transcoder enable function, and this is clearer, too. - Fixup 80 char line overflow in intel_display.c. I've opted to ignore this in i915_reg.h and i915_ums.c since meh. Cc: Paulo Zanoni <przanoni@gmail.com> Reviewed-by:
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Daniel Vetter authored
Every time I read hsw code I get completely confused about this. So call it what it is more explicitly. Also, add an LPT_TRANSCONF for the pch transcoder A and use it in lpt-only code, to really unconfuse me. v2: s/plane/pipe/ in the TRANSCONF #define (Paulo). Reviewed-by:
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Daniel Vetter authored
With the hw state readout&check code it's important that the values we keep around are the canonical ones. Unfortunately when adding the pipe timings readout support I've missed that the write side adjusts the timings in the pipe config. Fix this up and so prevent the unsightly WARN noise in dmesg. This regression has been introduced in commit 1bd1bd80 Author: Daniel Vetter <daniel.vetter@ffwll.ch> Date: Mon Apr 29 21:56:12 2013 +0200 drm/i915: hw state readout support for pipe timings Reported-by:
Paulo Zanoni <przanoni@gmail.com> Cc: Mika Kuoppala <mika.kuoppala@intel.com> Reviewed-by:
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Mika Kuoppala authored
Storing context reference into request struct allows us to inspect context and its associated objects when requests are retired. Both ppgtt and arb robustness work will need this. Signed-off-by:
Mika Kuoppala <mika.kuoppala@intel.com> Reviewed-by:
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Chris Wilson authored
In order to be notified of when the context and all of its associated objects is idle (for if the context maps to a ppgtt) we need a callback from the retire handler. We can arrange this by using the kref_get/put of the context for request tracking and by inserting a request to demarque the switch away from the old context. [Ben: fixed minor error to patch compile, AND s/last_context/from/] Signed-off-by:
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Daniel Vetter authored
dp_init_connector adjusts the encoder type if it is a eDP panel. Use that to decide whether we should set up a hdmi connector or not. To do so reorder the hdmi connector setup sequence in ddi_init a bit. Reviewed-by:
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- 03 May, 2013 2 commits
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Jesse Barnes authored
We can't read the pfit regs if the power well is off, so use the cached value. v2: re-add lost comment (Jesse) make sure the crtc using the fitter is actually enabled (Jesse) Signed-off-by: -
Mika Kuoppala authored
Before module unload is called, gpu_idle() will switch to default context. This will increment ref count of base object as the default context is 'running' on module unload time. Unreference the drm object so that when context is freed, base object is freed as well. v2: added comment to explain the refcounts (Ben Widawsky) Signed-off-by:
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- 02 May, 2013 1 commit
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Daniel Vetter authored
If we ever leak a non-DP compliant port width through here, we have a pretty serious issue. So just rip out all these WARNs - if we need them it's probably better to have them at a central place where we compute the dp lane count. Also use the new DDI width macro for FDI mode. Cc: Paulo Zanoni <paulo.r.zanoni@intel.com> Reviewed-by:
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- 30 Apr, 2013 2 commits
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Mika Kuoppala authored
Enabling PPGTT and also the need to track which context was guilty of gpu hang (arb robustness enabling) have put pressure for struct i915_hw_context to be more than just a placeholder for hw context state. In order to track object lifetime properly in a multi peer usage, add reference counting for i915_hw_context. v2: track i915_hw_context pointers instead of using ctx_ids (from Chris Wilson) v3 (Ben): Get rid of do_release() and handle refcounting more compactly. (recommended by Chis) v4: kref_* put inside static inlines (Daniel Vetter) remove code duplication on freeing context (Chris Wilson) v5: idr_remove and ctx->file_priv = NULL in destroy ioctl (Chris) This actually will cause a problem if one destroys a context and later refers to the idea of the context (multiple contexts may have the same id, but only 1 will exist in the idr). v6: Strip out the request related stuff. Reworded commit message. Got rid of do_destroy and introduced i915_gem_context_release_handle, suggested by Chris Wilson. v7: idr_remove can't be called inside idr_for_each (Chris Wilson) Signed-off-by: Ben Widawsky <ben@bwidawsk.net> (v5) Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com> (v7) Reviewed-by:
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Ville Syrjälä authored
Reduce the size of the the src/dst viewport to keep the scalign ratios in check. v2: Below min size sprite handling squashed to previous patch Reviewed-by:
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