- 17 Sep, 2019 1 commit
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Lyude Paul authored
On the ThinkPad P71, we have one eDP connector exposed along with 5 DP connectors, resulting in a total of 11 TMDS encoders. Since the GPU on this system is also capable of MST, we create an additional 4 fake MST encoders for each DP port. Unfortunately, we also do this for the eDP port as well, resulting in: 1 eDP port: +1 TMDS encoder +4 DPMST encoders 5 DP ports: +2 TMDS encoders +4 DPMST encoders *5 ports == 35 encoders Which breaks things, since DRM has a hard coded limit of 32 encoders. So, fix this by not creating MSTMs for any eDP connectors. This brings us down to 31 encoders, although we can do better. This fixes driver probing for nouveau on the ThinkPad P71. Signed-off-by:Lyude Paul <lyude@redhat.com> Cc: stable@vger.kernel.org Signed-off-by:
Ben Skeggs <bskeggs@redhat.com>
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- 06 Sep, 2019 2 commits
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https://git.pengutronix.de/git/lst/linuxDave Airlie authored
single etnaviv fix for an error path. Signed-off-by:
Dave Airlie <airlied@redhat.com> From: Lucas Stach <l.stach@pengutronix.de> Link: https://patchwork.freedesktop.org/patch/msgid/4ae00cfb47c8e6fffca5dbb45ae9370cd4e5eaf4.camel@pengutronix.de
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git://people.freedesktop.org/~agd5f/linuxDave Airlie authored
drm-next-5.4-2019-08-30: amdgpu: - Add DC support for Renoir - Add some GPUVM hw bug workarounds - add support for the smu11 i2c controller - GPU reset vram lost bug fixes - Navi1x powergating fixes - Navi12 power fixes - Renoir power fixes - Misc bug fixes and cleanups Signed-off-by:
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- 03 Sep, 2019 1 commit
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Dave Airlie authored
Merge tag 'exynos-drm-next-for-v5.4' of git://git.kernel.org/pub/scm/linux/kernel/git/daeinki/drm-exynos into drm-next - JUst one cleanup which drops the use of drmP.h header file. Signed-off-by:
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- 02 Sep, 2019 1 commit
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Wei Yongjun authored
Add the missing unlock before return from function etnaviv_iommuv1_context_alloc() in the error handling case. Fixes: 27b67278 ("drm/etnaviv: rework MMU handling") Signed-off-by:
Wei Yongjun <weiyongjun1@huawei.com> Signed-off-by:
Lucas Stach <l.stach@pengutronix.de>
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- 01 Sep, 2019 1 commit
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Sam Ravnborg authored
There was a few uses of drmP that was missed in the last patch removing this header from exynos. Remove the final uses of this header. Signed-off-by:
Sam Ravnborg <sam@ravnborg.org> Cc: Inki Dae <inki.dae@samsung.com> Cc: Joonyoung Shim <jy0922.shim@samsung.com> Cc: Seung-Woo Kim <sw0312.kim@samsung.com> Cc: Kyungmin Park <kyungmin.park@samsung.com> Cc: David Airlie <airlied@linux.ie> Cc: Daniel Vetter <daniel@ffwll.ch> Cc: Kukjin Kim <kgene@kernel.org> Cc: Krzysztof Kozlowski <krzk@kernel.org> Cc: Jingoo Han <jingoohan1@gmail.com> Signed-off-by:
Inki Dae <inki.dae@samsung.com>
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- 30 Aug, 2019 6 commits
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Austin Kim authored
Null pointer dereference check should have been checked, ahead of below routine. struct amdgpu_device *adev = hwmgr->adev; With this commit, it could avoid potential NULL dereference. Signed-off-by:
Austin Kim <austindh.kim@gmail.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Petr Cvek authored
There is missing "if defined" CONFIG_DRM_AMD_DC block for non DC configurations. This will cause link error. The patch is fixing that. Bug: https://bugs.freedesktop.org/show_bug.cgi?id=110979Signed-off-by:
Petr Cvek <petrcvekcz@gmail.com> Signed-off-by:
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Aaron Liu authored
In renoir's vega10_ih model, there's a security change in mmIH_CHICKEN register, that limits IH to use physical address (FBPA, GPA) directly. Those chicken bits need to be programmed first. Signed-off-by:
Aaron Liu <aaron.liu@amd.com> Reviewed-by:
Huang Rui <ray.huang@amd.com> Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com> Acked-by:
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Aaron Liu authored
In Renoir's emulator, those chicken bits need to be programmed. Signed-off-by:
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Aaron Liu authored
For apu, SMU_MSG_OverridePcieParameters is unsupport. So return directly in smu_override_pcie_parameters function. Signed-off-by:
Evan Quan <evan.quan@amd.com> Acked-by:
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Andrey Grodzovsky authored
This should be checked at all places job is accessed. Signed-off-by:
Andrey Grodzovsky <andrey.grodzovsky@amd.com> Reviewed-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
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- 29 Aug, 2019 28 commits
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Roman Li authored
Enable DC support for renoir. Acked-by:
Harry Wentland <harry.wentland@amd.com> Signed-off-by:
Roman Li <Roman.Li@amd.com> Signed-off-by:
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Roman Li authored
Hook up the DML changes for renoir. Acked-by:
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Roman Li authored
Need to check for renoir first. Acked-by:
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Bhawanpreet Lakha authored
Add a kconfig option to enable renoir. Acked-by:
Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by:
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Bhawanpreet Lakha authored
Enable the building of dcn21 support. Acked-by:
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Bhawanpreet Lakha authored
Add missing parameters, to make dcn21 compile without errors Acked-by:
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Bhawanpreet Lakha authored
Add the rev id for renoir. Acked-by:
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Bhawanpreet Lakha authored
call update_bw_bounding_box in DC construct Acked-by:
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Bhawanpreet Lakha authored
Hook up renoir support to KMS. v2: squash in "Fixes for Renoir in amdgpu_dm" Acked-by:
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Bhawanpreet Lakha authored
add Renoir DCN version in DC and handle it Acked-by:
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Bhawanpreet Lakha authored
rename VM_CONTEXT0 to MMVM_CONTEXT0 as that is the name defined in the register files Acked-by:
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Bhawanpreet Lakha authored
DML provides the display configuration validation as provided by the hw teams. Acked-by:
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Bhawanpreet Lakha authored
Misc display related configuration details. Acked-by:
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Bhawanpreet Lakha authored
Manages the renoir display resources (crtcs, phys, plls, etc.). v2: rebase (Alex) Acked-by:
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Bhawanpreet Lakha authored
Controls display clocks and interfaces with powerplay for clock and power requirements. Acked-by:
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Bhawanpreet Lakha authored
Controls the display hw's interface to memory. v2: rebase (Alex) Acked-by:
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Bhawanpreet Lakha authored
These are the registers used to program the hubbub hw. Acked-by:
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Bhawanpreet Lakha authored
This provides the interface to memory for the display hw. v2: minor cleanup (Alex) Acked-by:
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Bhawanpreet Lakha authored
Provides the interface to configure display interrrupts on renoir. v2: rebase fix (Alex) Acked-by:
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Bhawanpreet Lakha authored
This defines the interface for communicating requirements between DC and powerplay. Acked-by:
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Bhawanpreet Lakha authored
These are the registers used to for the hw sequences for modesetting. Acked-by:
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Bhawanpreet Lakha authored
These are the registers used to program the clock hw. Acked-by:
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Bhawanpreet Lakha authored
add registers for dcn, clk, and renoir ip offsets v2: header cleanup (Alex) v3: Add DPCS registers (Hersen) Acked-by:
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Prike Liang authored
add the get_dpm_ultimate_freq for supporting different swSMU. -v2: Handle the unsupported clock type and read smc message failed case and return error code. Move the smu12 uclk frequency retrieved logic to renoir ppt. -v3: Use goto clause to handle invalidate clk index. Add the limited tag for smu_get_dpm_uclk to avoid other likewise interface introduced. Signed-off-by:Prike Liang <Prike.Liang@amd.com> Reviewed-by:
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Prike Liang authored
Should populate DPM clocks tables during hw init,otherwise will suffer from invalidate table. Signed-off-by:
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Prike Liang authored
There is no driver message to enable/disable feature mask for APU. For the sake of APU reusing swSMU interface and assume APU supports all the feature. Signed-off-by:
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Prike Liang authored
Init SDMA HW base configuration and enable idle INT for rn. Signed-off-by:
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Tianci.Yin authored
Fix compute ring test failure in sriov scenario. Reviewed-by:
Tianci.Yin <tianci.yin@amd.com> Signed-off-by:
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