- 31 May, 2019 28 commits
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Krunoslav Kovac authored
[Why] There's some unnecessary mem allocation for CS_TFM_ID. What's worse, it depends on LUT size and since it's 4K for CS_TFM_1D, it is 16x bigger than in regular case when it's actually needed. This leads to some crashes in stress conditions. [How] Skip ramp combining designed for RGB256 and DXGI gamma with CS_TFM_1D. Signed-off-by:
Krunoslav Kovac <Krunoslav.Kovac@amd.com> Reviewed-by:
Aric Cyr <Aric.Cyr@amd.com> Acked-by:
Leo Li <sunpeng.li@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Nicholas Kazlauskas authored
[Why] For commits with allow_modeset=false and CRTC degamma changes the planes aren't reset. This results in incorrect rendering. [How] Reset the planes when color management has changed on the CRTC. Technically this will include regamma changes as well, but it doesn't really after legacy userspace since those commit with allow_modeset=true. Signed-off-by:
Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Reviewed-by:
Harry Wentland <Harry.Wentland@amd.com> Acked-by:
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Eryk Brol authored
[Why] Some backlight tests fail due to backlight settling taking too long. This happens because the step size used to change backlight levels is too small. [How] 1. Change the size of the backlight gain step size 2. Change how DMCU firmware gets the step size value so that it is passed in by driver during DMCU initn Signed-off-by:
Eryk Brol <eryk.brol@amd.com> Reviewed-by:
Jun Lei <Jun.Lei@amd.com> Acked-by:
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Anthony Koo authored
[Why] Some displays take some time to power up AUX CH once they are put into D3 state via write to DPCD 600h=2. Interestingly enough, some display may simply NACK, but some might also ACK with a bunch of 0s, which can cause issues with receiver cap retrieval. Note that not all DPCD address return 0s, but in particular it has been observed on some higher DPCD address such as DPCD 2200h, etc. [How] Based on spec, receiver will monitor differential signal while in D3 and AUX CH is in low power mode. When detected, it may allow up to 1 ms to power up AUX CH and reply. If we read Sink power state D3, we should add 1 ms delay to satisfy this spec requirement. Signed-off-by:
Anthony Koo <anthony.koo@amd.com> Reviewed-by:
Wenjing Liu <Wenjing.Liu@amd.com> Acked-by:
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Eric Bernstein authored
* Pull duplicate audio_clock_info struct to stream_encoder.h * Generalize sec_gsp7* to sec_gsp_pps* * Expose enc1 and enc2 stream encoder audio funcs Signed-off-by:
Eric Bernstein <eric.bernstein@amd.com> Reviewed-by:
Charlene Liu <Charlene.Liu@amd.com> Reviewed-by:
Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Acked-by:
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Daniel He authored
[Description] This is cause by failing to read link caps from driver. Signed-off-by:
Daniel He <daniel.he@amd.com> Reviewed-by:
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Ilya Bakoulin authored
Adding writeback_config enum to vba_vars_st, replacing old flag. Initialize to dm_normal. Signed-off-by:
Ilya Bakoulin <Ilya.Bakoulin@amd.com> Reviewed-by:
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Eric Yang authored
[Why] Some HW specific implementations can be pulled out into clk_mgr.c. [How] * Pull get_active_display_cnt out to clk_mgr. * Pull out shared logic in set_dispclk and set_dprefclk Signed-off-by:
Eric Yang <Eric.Yang2@amd.com> Reviewed-by:
Tony Cheng <Tony.Cheng@amd.com> Acked-by:
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Eric Yang authored
[why] Value read from SMU is 16 bits, not 32. [How] Fix type, and add wm_type enum in preparation for future interfaces. Signed-off-by:
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Anthony Koo authored
[Why] Modern Standby may toggle display adapter state between D0 and D3 state unpredictably. But events that cause transition to D0 are not always resulting in a display light up scenario. Modern eDP panels should be able to power on panel logic quickly upon VDD going high. Based on spec, the T3 time between VDD on and HPD high can be between 0 and 80 ms. Doing any tricky sorts of optimization by powering on panel VDD early during D0 transition on can negatively impact other features due to unnecessary power drain and toggling when final system state does not intend for the panel to be lit up. We need OEMs to source higher end panels that have T3 time close to 0 if they want quick S3/Modern Standby resume times. [How] Remove panel VDD power on in init_hw Signed-off-by:
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Su Sung Chung authored
[why] during It's possible to call dcn_validate_bandwidth with no plane. In that case, as we are only intersted in if output timing is supported or not, even if we cannot support native resolution, we still want to support lower resolution if it is valid [how] if there exist no surface, make viewport/rec_out size at max 1080p. It is already known that 1080p x 6(max # of pipes) is supported, so if we fail validation, it is because of the stream Signed-off-by:
Su Sung Chung <Su.Chung@amd.com> Reviewed-by:
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Su Sung Chung authored
[why] by adding fast_validate flag, we are skipping some portion of dcn_validate_bandwidth code that is not necessary for mode validation. However we have a bug where it does not calculate v->total_data_read_bandwidth, which is one of the factors determines the result of the validation, and therefore report false positive during mode validation. [how] add calculation of v->total_data_read_bandwidth outside of the region that is guarded by fast_validate flag Signed-off-by:
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Aric Cyr authored
Signed-off-by:
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Chris Park authored
[Why] link-specific functions should reside in dc_link.c [How] Move them there. Signed-off-by:
Chris Park <Chris.Park@amd.com> Reviewed-by:
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Jun Lei authored
Add min_dcfclk_mhz to bounding box overrides. Signed-off-by:
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Eric Yang authored
[Why] Better organization [How] Move clk_mgr files under dc/clk_mgr Signed-off-by:
Yongqiang Sun <yongqiang.sun@amd.com> Acked-by:
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Paul Hsieh authored
[Why] 1. DMCU is not running on some platform but driver still send ABM command. It may cause assert due to DMCU is not alive. 2. To make sure PSR disable when driver disable [How] 1. Add dmcu_is_running in ABM struct, driver can check this flag to determine driver should send ABM command or not. 2. Send PSR disable command when destroy PSR Signed-off-by:
Paul Hsieh <paul.hsieh@amd.com> Reviewed-by:
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Eryk Brol authored
[Why] In the previous implementation DRR event sometimes came in during FP2 region which is a keep-out zone. This would cause the frame not to latch until the next frame which resulted in heavy flicker. To fix this we need to make sure that it triggers in the BP. [How] 1. Remove DRR programming during flip 2. Setup manual trigger for DRR event and trigger it after surface programming is complete Signed-off-by:
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Krunoslav Kovac authored
GSL is a form of locking that can be used to synchronize pipes in a pipe-split configurations when async flip is used. Add the registers here. Signed-off-by:
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Eryk Brol authored
[Why] Previously there were 2 consecutive calls being made to disable audio stream. The first one disabled the audio stream, and the second one went through and also tried to disable the audio stream causing BACO entry issues due to the ASIC appearing busy. [How] 1. Add a status field to the audio struct which stores enabled/disabled info 2. In the calls to enable/disable audio stream check if we're already in the desired state before executing the function Signed-off-by:
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Wenjing Liu authored
[why] stream id should uniquely identify an instance of stream. the copy constructor should be treated as a new stream instance. [how] assign a new stream id in this copy constructor. Signed-off-by:
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Eric Yang authored
This macro is specificly used by RV1. Move it to the appropriate location. Signed-off-by:
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Gary Kattan authored
Add vtable entries for de-alpha and bias color management interfaces. Move piece-wise transfer function registers to a helper list for future reuse. Signed-off-by:
Gary Kattan <gary.kattan@amd.com> Reviewed-by:
Nevenko Stupar <Nevenko.Stupar@amd.com> Acked-by:
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Hugo Hu authored
We can’t use hardcoded SRGB ROM for output TF if we have GAMMA_CS_TFM_1D (unless we know 1D LUT is identity), so we never want to return here early. We apply the LUT part of ColorTransform3x4 only in apply_lut_1d() which is called near the end of that function. Signed-off-by:
Hugo Hu <hugo.hu@amd.com> Reviewed-by:
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Eric Yang authored
[Why] First step of refactoring clk mgr to better handle different ways of handling clock operations. Clock operation policies are soc specific and not just DCN vesion specific. It is not a hw resource, should not be in the resource pool. [How] Change clock manager creation to be based on HW internal ID, rename clock manager members to be more clear. Move clock manager out of resource. Signed-off-by:
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Emily Deng authored
As it will destroy clear_state_obj, and also will unpin it in the gfx_v9_0_sw_fini, so don't need to call amdgpu_bo_free_kernel in gfx_v9_0_sw_fini, or it will have unpin warning. Signed-off-by:
Emily Deng <Emily.Deng@amd.com> Reviewed-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
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xinhui pan authored
injection need a valid gpu address. Signed-off-by:
xinhui pan <xinhui.pan@amd.com> Reviewed-by:
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git://people.freedesktop.org/~agd5f/linuxDave Airlie authored
New stuff for 5.3: - Add new thermal sensors for vega asics - Various RAS fixes - Add sysfs interface for memory interface utilization - Use HMM rather than mmu notifier for user pages - Expose xgmi topology via kfd - SR-IOV fixes - Fixes for manual driver reload - Add unique identifier for vega asics - Clean up user fence handling with UVD/VCE/VCN blocks - Convert DC to use core bpc attribute rather than a custom one - Add GWS support for KFD - Vega powerplay improvements - Add CRC support for DCE 12 - SR-IOV support for new security policy - Various cleanups From: Alex Deucher <alexdeucher@gmail.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190529220944.14464-1-alexander.deucher@amd.com
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- 29 May, 2019 1 commit
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Colin Ian King authored
The pointer dev is set to null yet it is being dereferenced when checking dev->dqm->sched_policy. Fix this by performing the check on dev->dqm->sched_policy after dev has been assigned and null checked. Also remove the redundant null assignment to dev. Addresses-Coverity: ("Explicit null dereference") Fixes: 1a058c33 ("drm/amdkfd: New IOCTL to allocate queue GWS") Signed-off-by:Colin Ian King <colin.king@canonical.com> Signed-off-by:
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- 28 May, 2019 11 commits
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Emily Deng authored
For passthrough, after rebooted the VM, driver will do a baco reset before doing other driver initialization during loading driver. For doing the baco reset, it will first check the baco reset capability. So first need to set the cap from the vbios information or baco reset won't be enabled. Signed-off-by:
Evan Quan <evan.quan@amd.com> Signed-off-by:
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Alex Deucher authored
Not necessary on soc15 and breaks driver reload on server cards. Acked-by:
Amber Lin <Amber.Lin@amd.com> Signed-off-by:
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Chunming Zhou authored
Reviewed-by:
Chunming Zhou <david1.zhou@amd.com> Reviewed-by:
Flora Cui <Flora.Cui@amd.com> Signed-off-by:
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Oak Zeng authored
Add a field in map_queues packet to indicate whether this is a gws control queue. Only one queue per process can be gws control queue. Change num_gws field in map_process packet to 7 bits Signed-off-by:
Oak Zeng <Oak.Zeng@amd.com> Reviewed-by:
Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by:
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Oak Zeng authored
Add a new kfd ioctl to allocate queue GWS. Queue GWS is released on queue destroy. Signed-off-by:
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Oak Zeng authored
Add functions in process queue manager to set/unset queue gws. Also set process's number of gws used. Currently only one queue in process can use and use all gws. Signed-off-by:
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Oak Zeng authored
GWS bo is shared between all kfd processes. Add function to add gws to kfd process's bo list so gws can be evicted from and restored for process. Signed-off-by:
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Oak Zeng authored
On device initialization, KFD allocates all (64) gws which is shared by all KFD processes. Signed-off-by:
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Oak Zeng authored
Add amdgpu_amdkfd interface to alloc and free gws from amdgpu Signed-off-by:
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Oak Zeng authored
Add amdgpu_amdkfd interface to get num_gws and add num_gws to /sys/class/kfd/kfd/topology/nodes/x/properties. Only report num_gws if MEC FW support GWS barriers. Currently it is determined by a module parameter which will be replaced with MEC FW version check when firmware is ready. Signed-off-by:
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Oak Zeng authored
TTM doesn't support CPU mapping of sg type bo (under which mmio bo is created). Switch mmaping of mmio page to kfd device file. Signed-off-by:
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