- 12 Apr, 2024 1 commit
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Luqmaan Irshad authored
Adding a new field for GPU Capacity to align the header with the host. Signed-off-by:
Luqmaan Irshad <Luqmaan.Irshad@amd.com> Acked-by:
Alex Deucher <alexander.deucher@amd.com> Signed-off-by:
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- 10 Apr, 2024 39 commits
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Yifan Zhang authored
This patch to differentiate external rev id for gfx 11.5.0. Signed-off-by:
Yifan Zhang <yifan1.zhang@amd.com> Reviewed-by:
Tim Huang <Tim.Huang@amd.com> Signed-off-by:
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Xiang Yang authored
the dram_clock_change_latency_us in dcn3_51_soc is initialized twice, so delete one of them. Acked-by:
Xiang Yang <xiangyang3@huawei.com> Signed-off-by:
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Simon Horman authored
The path to GPU documentation is Documentation/gpu rather than Documentation/GPU This appears to have been introduced by commit ba162ae7 ("Documentation/gpu: Introduce a simple contribution list for display code") Flagged by make htmldocs. Signed-off-by:
Simon Horman <horms@kernel.org> Signed-off-by:
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Erick Archer authored
This is an effort to get rid of all multiplications from allocation functions in order to prevent integer overflows [1] [2]. In this case, the memory allocated to store RADEONFB_CONN_LIMIT pointers to "drm_connector" structures can be avoided. This is because this memory area is never accessed. Also, in the kzalloc function, it is preferred to use sizeof(*pointer) instead of sizeof(type) due to the type of the variable can change and one needs not change the former (unlike the latter). At the same time take advantage to remove the "#if 0" block, the code where the removed memory area was accessed, and the RADEONFB_CONN_LIMIT constant due to now is never used. Link: https://www.kernel.org/doc/html/latest/process/deprecated.html#open-coded-arithmetic-in-allocator-arguments [1] Link: https://github.com/KSPP/linux/issues/160 [2] Acked-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
Erick Archer <erick.archer@outlook.com> Signed-off-by:
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Rodrigo Siqueira authored
DCN10 OPTC is used by other DCNs, and in some cases it might be useful to have V_TOTAL_REGS available. This commit add V_TOTAL_REGS as part of the TG field. Acked-by:
Hamza Mahfooz <hamza.mahfooz@amd.com> Signed-off-by:
Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by:
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Anthony Koo authored
- Add boot option to change the ONO powerup flow, impacting the order of power domains to power up or down first Acked-by:
Anthony Koo <anthony.koo@amd.com> Signed-off-by:
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Qili Lu authored
This reverts commit b72a7e0f. It causes a dead loop in dml_prefetch_check. Reviewed-by:
Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Acked-by:
Qili Lu <qili.lu@amd.com> Signed-off-by:
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George Shen authored
[Why] For video mode test pattern (i.e. test pattern disable), the call to rebuild test pattern params for the pipe is skipped. This causes dynamic disablement of test pattern to not work, as the test_pattern_params of the pipe will not be updated and retain the values of the previously enabled test pattern. [How] Rebuild test pattern params even when test pattern is video mode, allowing the pipe to have updated test_pattern_params values. Reviewed-by:
Nevenko Stupar <nevenko.stupar@amd.com> Reviewed-by:
Chaitanya Dhere <chaitanya.dhere@amd.com> Acked-by:
George Shen <george.shen@amd.com> Signed-off-by:
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Zhongwei authored
[Why] OLED panels show no display for large vtotal timings. [How] Check if ss is enabled and read from lut for spread spectrum percentage. Adjust dprefclk as required. DP_DTO adjustment is for edp only. Cc: stable@vger.kernel.org Reviewed-by:
Zhongwei <zhongwei.zhang@amd.com> Signed-off-by:
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Harry Wentland authored
The previous check for the is_vsc_sdp_colorimetry_supported flag for MST sink signals did nothing. Simplify the code and use the same check for MST and SST. Cc: stable@vger.kernel.org Reviewed-by:
Agustin Gutierrez <agustin.gutierrez@amd.com> Acked-by:
Harry Wentland <harry.wentland@amd.com> Signed-off-by:
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Harry Wentland authored
In order for display colorimetry to work correctly on DP displays we need to send the VSC SDP packet. We should only do so for panels with DPCD revision greater or equal to 1.4 as older receivers might have problems with it. Cc: stable@vger.kernel.org Cc: Joshua Ashton <joshua@froggi.es> Cc: Xaver Hugl <xaver.hugl@gmail.com> Cc: Melissa Wen <mwen@igalia.com> Cc: Agustin Gutierrez <Agustin.Gutierrez@amd.com> Reviewed-by:
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Charlene Liu authored
[why] dwb was not POR previosly. now need to enable dwb in dml2. Limitation: HW DML assumes only one DWB one set of watermark for all 4 watermark sets one stream has one DWB only. WB scaling dml input has one set of scaling tap. (no chroma so far) needs to follow up Reviewed-by:
Chris Park <chris.park@amd.com> Acked-by:
Charlene Liu <charlene.liu@amd.com> Signed-off-by:
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Parandhaman K authored
why and how: as part of cleanup, need to refactor vpg. It was improperly referenced as a dcn specfic part of link. the dcn agnostic code needed was ripped out and put into vpg.h, now in dc/inc/hw. Reviewed-by:
Alvin Lee <alvin.lee2@amd.com> Acked-by:
Parandhaman K <parandhaman.k@amd.com> Signed-off-by:
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Allen Pan authored
[Why] 6.75 Gbps link rate training for DP_TEST_LINK_RATE_RATE_8 Reviewed-by:
Allen Pan <allen.pan@amd.com> Signed-off-by:
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Fudongwang authored
[Why] Wrong logic cause screen corruption. [How] Port logic from DCN35/314. Cc: stable@vger.kernel.org Reviewed-by:
Fudongwang <fudong.wang@amd.com> Signed-off-by:
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Dillon Varone authored
[WHY&HOW] We should not be recursively calling the manual trigger programming function when FAMS is not in use. Cc: stable@vger.kernel.org Reviewed-by:
Dillon Varone <dillon.varone@amd.com> Signed-off-by:
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Dillon Varone authored
[WHY&HOW] Changes to support future versions of FAMS. Reviewed-by:
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Lijo Lazar authored
Setting soft max frequency for MCLK is allowed in 1VF mode in SMUv13.0.6 SOCs. Signed-off-by:
Lijo Lazar <lijo.lazar@amd.com> Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
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Wenjing Liu authored
[why] When Subvp pipe's index is smaller than main pipe's index, the main pipe's ODM policy is not yet assigned. If we assign subvp pipe's ODM policy based on main pipe, we will assign uninitialized ODM policy. [how] Instead of copying main pipe's policy we copy the main pipe ODM policy logic. So it doesn't matter whether if main pipe's ODM policy is set, phantom pipe will always have the same policy because it running the same calcualtion to derive ODM policy. Cc: stable@vger.kernel.org Reviewed-by:
Wenjing Liu <wenjing.liu@amd.com> Signed-off-by:
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Wenjing Liu authored
[why] In current implemenation ODM mode is only reset when the last plane is removed from dc state. For any dc validate we will always remove all current planes and add new planes. However when switching from no planes to 1 plane, ODM mode is not reset because no planes get removed. This has caused an issue where we kept ODM combine when it should have been remove when a plane is added. The change is to reset ODM mode when adding the first plane. Cc: stable@vger.kernel.org Reviewed-by:
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Tim Huang authored
The RB bitmap should be global active RB bitmap & active RB bitmap based on active SA. Signed-off-by:
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Alex Hung authored
mode_config's max width x height is 4096x2160 and is higher than DWB's max resolution 3840x2160 which is returned instead. Cc: stable@vger.kernel.org Reviewed-by:
Alex Hung <alex.hung@amd.com> Signed-off-by:
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Lewis Huang authored
[Why] We want flexibility to choose how pwrseq instance is mapped to eDP panel [How] Add configuration option to choose the pwrseq mapping policy. When enabled, allow fixed mapping between DIG inst to pwrseq inst. Reviewed-by:
Lewis Huang <lewis.huang@amd.com> Signed-off-by:
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Zhigang Luo authored
1. change AMDGPU_VF2PF_UPDATE_MAX_RETRY_LIMIT from 30 to 5. 2. set fatel error detected flag. Signed-off-by:
Zhigang Luo <Zhigang.Luo@amd.com> Reviewed-by:
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Zhigang Luo authored
If there are more than one device doing reset in parallel, the first device will call kfd_suspend_all_processes() to evict all processes on all devices, this call takes time to finish. other device will start reset and recover without waiting. if the process has not been evicted before doing recover, it will be restored, then caused page fault. Signed-off-by:
Felix Kuehling <felix.kuehling@amd.com> Signed-off-by:
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Lijo Lazar authored
Set RAS priority handling capability for SMUv13.0.6 SOCs and categorize RAS priority messages allowed. Signed-off-by:
Asad Kamal <asad.kamal@amd.com> Signed-off-by:
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Lijo Lazar authored
When a RAS fatal error is detected, PMFW will only process priority messages. Other messages won't be taken up for processing and therefore won't get any response in such a state. Add logic to filter out non-priority messages when RAS error is detected. Also, don't poll response response status register before sending priority messages. Use firmware capability flag to determine whether to filter priority messages. Signed-off-by:
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Lijo Lazar authored
Add flags to categorize messages and PMFW capabilities. Signed-off-by:
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Lijo Lazar authored
In case of fatal errors, set FED status when interrupt is received. Set the flag on other devices in the hive before RAS recovery work. Signed-off-by:
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Srinivasan Shanmugam authored
This commit removes the lines that describe the 'streams' and 'stream_count' parameters and adds a line to describe the 'params' parameter, which was missing from the original comment block. Fixes the below with gcc W=1: drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc.c:2138: warning: Function parameter or member 'params' not described in 'dc_commit_streams' drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc.c:2138: warning: Excess function parameter 'streams' description in 'dc_commit_streams' drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc.c:2138: warning: Excess function parameter 'stream_count' description in 'dc_commit_streams' Fixes: e779f458 ("drm/amd/display: Add handling for DC power mode") Cc: Joshua Aberback <joshua.aberback@amd.com> Cc: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Cc: Roman Li <roman.li@amd.com> Cc: Aurabindo Pillai <aurabindo.pillai@amd.com> Cc: Tom Chung <chiahsuan.chung@amd.com> Signed-off-by:
Srinivasan Shanmugam <srinivasan.shanmugam@amd.com> Reviewed-by:
Tom Chung <chiahsuan.chung@amd.com> Signed-off-by:
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Asad Kamal authored
Use OD (pp_od_clk_voltage) interface to report current limits, default or those set by user, for SCLK and UCLK on aldebaran. Signed-off-by:
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Asad Kamal authored
Use OD (pp_od_clk_voltage) interface to report current limits, default or those set by user, for SCLK and UCLK on smu_v_13_0_6 Signed-off-by:
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ZhenGuo Yin authored
[Why] set_q_mode_offs don't get cleared after GPU reset, nexting SET_Q_MODE packet to init shadow memory will be skiped, hence there has a page fault. [How] VM flush is needed after GPU reset, clear set_q_mode_offs when emitting VM flush. Fixes: 8bc75586 ("drm/amdgpu: workaround to avoid SET_Q_MODE packets v2") Reviewed-by:
ZhenGuo Yin <zhenguo.yin@amd.com> Signed-off-by:
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Tao Zhou authored
RAS TA will handle it, the function is useless. Signed-off-by:
Tao Zhou <tao.zhou1@amd.com> Reviewed-by:
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chongli2 authored
support MES command SET_HW_RESOURCE1 in sriov Signed-off-by:
chongli2 <chongli2@amd.com> Reviewed-by:
Jingwen Chen <Jingwen.Chen2@amd.com> Acked-by:
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Tao Zhou authored
Check more possible ext error codes. Signed-off-by:
Yang Wang <kevinyang.wang@amd.com> Signed-off-by:
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Tao Zhou authored
Add more possible ext error code. v2: still use ext error code instead of UC bit. Signed-off-by:
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Lijo Lazar authored
VCN need not be shared in CPX mode always for all GFX 9.4.3 SOC SKUs. In certain configs, VCN instance can be exclusively allocated to a partition even under CPX mode. Signed-off-by:
James Zhu <James.Zhu@amd.com> Reviewed-by:
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Ma Jun authored
Check AMDGPU_RUNPM_BAMACO intead of amdgpu_runtime_pm when setting baco state. Signed-off-by:
Ma Jun <Jun.Ma2@amd.com> Reviewed-by:
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