- 09 Oct, 2018 31 commits
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Nicholas Kazlauskas authored
[Why] The DISPCLK value was previously requested to be 15% higher for all ASICS that went through the dce110 bandwidth code path. As part of a refactoring of dce_clocks and dce110 set_bandwidth this was removed for power saving considerations. This changed caused corruption under certain display configurations. Originally thought to be Vega specific, it was also observed on Polaris. [How] The 15% is brought back but its placement differs from the original patch. This boost should only be enable while DFS bypass is inactive. This (like the Vega patch) is also a workaround that should be removed after the root cause is identified. Signed-off-by:
Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Reviewed-by:
Harry Wentland <Harry.Wentland@amd.com> Acked-by:
Leo Li <sunpeng.li@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Murton Liu authored
[Why] Due to a small pre-fetch window, the active vline timing is a couple of lines off when compared to what it should be. [How] Changed the calculation for the start vline to account for this window. Signed-off-by:
Murton Liu <murton.liu@amd.com> Reviewed-by:
Aric Cyr <Aric.Cyr@amd.com> Acked-by:
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Charlene Liu authored
[Description] interlace mode shows wrong vertical timing. Interface timing in Edid is half vertical timing as progressive timing. driver doubled the vertical timing in edid_paser, no need to double in optc again. Signed-off-by:
Charlene Liu <charlene.liu@amd.com> Reviewed-by:
Chris Park <Chris.Park@amd.com> Acked-by:
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Leo Li authored
[Why] There is no reason why the common data needs to be kept separate. [How] Flatten the struct by moving common data into the DM IRQ struct. Signed-off-by:
David Francis <David.Francis@amd.com> Acked-by:
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Jun Lei authored
[why] ddc engines were recently changed to be independently tracked from pipe count. the change was reflected in resource constructor but not in destructor. this manifests as a memory leak when pipe harvesting is enabled, since not all constructed ddc engines are freed [how] make destructor symmetric with constructor for all dcX_resource Signed-off-by:
Jun Lei <Jun.Lei@amd.com> Reviewed-by:
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Tony Cheng authored
Signed-off-by:
Tony Cheng <tony.cheng@amd.com> Reviewed-by:
Steven Chiu <Steven.Chiu@amd.com> Acked-by:
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Yongqiang Sun authored
[Why] DF keeps awake after S0i3 resume due to DRAM_STATE_CNTL is set by bios command table during dcn init_hw. [How] As a work around, check STATE_CNTL status before init_hw, if it is 0 before init_hw and set to 1 after init_hw, change it to 0. Signed-off-by:
Yongqiang Sun <yongqiang.sun@amd.com> Reviewed-by:
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Eric Yang authored
[Why] All ASICS we support has YCbCr support, so the check is unnecessary, the currently logic in validate output also returns true all the time, so the unneccessary logic is removed Signed-off-by:
Eric Yang <Eric.Yang2@amd.com> Reviewed-by:
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Eric Yang authored
[why] Currently not supported, will black screen when set. [How] Fail validate timing helper for those modes. Signed-off-by:
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Eryk Brol authored
Also add dram clock to clocks struct, for systems that uses them. Signed-off-by:
Eryk Brol <eryk.brol@amd.com> Reviewed-by:
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Su Sung Chung authored
[Why] Previously bandwidth validation was failing because swizzle mode was not initialized during plane_state allocation. The swizzle mode was calculated using pixed format which is how swizzle mode is initially calculated in addrlib. [How] * Set default swizzle mode for validation to DC_SW_UNKNOWN * Created new function in dcn10_assign_swizzle_mode which sets the plane swizzle mode based on selected pixed format * Added the call of assign_swizzle_mode into dc_validate_global_state * Set failsafe swizzle mode back to DC_SW_LINEAR Signed-off-by:
Su Sung Chung <Su.Chung@amd.com> Reviewed-by:
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Nikola Cornij authored
[why] Same functions exist for all other signal types. [how] Add a function that checks against virtual signal type. Signed-off-by:
Nikola Cornij <nikola.cornij@amd.com> Reviewed-by:
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Charlene Liu authored
[Why] HDMI_scramber is not enabled for pixel rate >340Mhz. [How] Calculate the phy clock to include the Hw frame packing factor. Signed-off-by:
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Jun Lei authored
[why] Sometimes there are indications that the incorrect driver is being loaded in automated tests. This change adds the ability for builds to be tagged with a string, and picked up by the test infrastructure. [how] dc.c will allocate const for build id, which is init-ed with default value, indicating production build. For test builds, build server will find/replace this value. The test machine will then verify this value. Signed-off-by:
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Akshu Agrawal authored
We observe black lines (underflow) on display when playing a 4K video with UVD. On Disabling Low memory P state this issue is not seen. Multiple runs of power measurement shows no imapct. Signed-off-by:
Akshu Agrawal <akshu.agrawal@amd.com> Signed-off-by:
Satyajit Sahu <satyajit.sahu@amd.com> Acked-by:
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Rex Zhu authored
HW CG feature will be enabled after hw ip initialized Reviewed-by:
Rex Zhu <Rex.Zhu@amd.com> Signed-off-by:
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Rex Zhu authored
the vcn power will be controlled by VCN. Reviewed-by:
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Rex Zhu authored
smu only expose interface to other ip blocks. in order to reduce dependence between smu and other ip blocks Reviewed-by:
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Rex Zhu authored
SDMA IP can be power up/down via smu message Reviewed-by:
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Rex Zhu authored
The minRPM speed maybe equal to zero. so need to check input RPM not equal to 0, otherwise cause divide-by-zero driver crash. Reviewed-by:
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Rex Zhu authored
set the target rpm value to wrong register. Reviewed-by:
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Rex Zhu authored
Reviewed-by:
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Evan Quan authored
Added Vega20 specific implementation for MGPU fan boost feature. Signed-off-by:
Evan Quan <evan.quan@amd.com> Reviewed-by:
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Evan Quan authored
MGPU fan boost feature is enabled only when two or more dGPUs in the system. Signed-off-by:
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Evan Quan authored
Count all GPU instances from AMD(including iGPUs and dGPUs) in the system. V2: drop unnecessary initialization for other gpu_info members except mutex Signed-off-by: -
Alex Deucher authored
Make the profile name line match previous generations more closely. E.g., 0 3D_FULL_SCREEN : vs: 0(3D_FULL_SCREEN ) Reviewed-by:
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Evan Quan authored
For Vega10 and Vega20, the always on CUs are 12. For Raven, it's 4. Signed-off-by:
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Evan Quan authored
Enable LBPW support on vega20. v2: squash in warning fix (Alex) Signed-off-by:
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Evan Quan authored
Manual fan RPM and pwm setting on vega20 are available now. V2: correct the register for fan speed setting and avoid divide-by-zero Signed-off-by: -
Evan Quan authored
Export the correct gfx voltage by hwmon interface. V2: update the register naming for consistency Signed-off-by:
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Evan Quan authored
The ppt limit read out by hwmon interface is always 0. Correct this hwmon interface output. Signed-off-by:
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- 04 Oct, 2018 7 commits
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git://linux-arm.org/linux-ldDave Airlie authored
misc mali-dp updates. Signed-off-by:
Dave Airlie <airlied@redhat.com> From: Liviu Dudau <Liviu.Dudau@arm.com> Link: https://patchwork.freedesktop.org/patch/msgid/20181003105009.GD1156@e110455-lin.cambridge.arm.com
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https://github.com/jsarha/linuxDave Airlie authored
drm/tilcdc changes for Linux v4.20 suspend/resume update. Signed-off-by:
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Dave Airlie authored
I have some pulls based on rc6, and I prefer to have an explicit backmerge. Signed-off-by: -
Dave Airlie authored
Merge tag 'exynos-drm-next-for-v4.20' of git://git.kernel.org/pub/scm/linux/kernel/git/daeinki/drm-exynos into drm-next Add out-bridge support - This patch series enables out-bridge for LVDS bridge device support, and also includes two cleanups and one relevant dt binding update for this. Add Samsung 16x16 tiled format support - This patch series adds Samsung 16x16 tiled format to scaler and gsc drivers. As for this, it adds Samsung specific format to drm_forcc.h header. For the git-pull request with relevant patches, I requested ack-by[1] to relevant maintainers but there was no any response. I'm pretty sure no problem to go to mainline though Exynos tree because the only user of it is Exynos. (airlied: this looked fine to me) [1] https://patchwork.freedesktop.org/patch/243921/ Add configurable plane alpha and pixel blend mode support - This patch series makes mixer driver to be configuragle for pixel blend mode and plane alpha, which also includes one fixup to set all default values correctly after reset. One cleanup - This patch replaces drm_atomic_helper_suspend/resume() with drm_mode_config_helper_suspend/resume() to remove exynos specific suspend_state. Signed-off-by:
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Dave Airlie authored
Merge tag 'omapdrm-4.20-2' of git://git.kernel.org/pub/scm/linux/kernel/git/tomba/linux into drm-next omapdrm fixes and cleanups for 4.20 - fix memory barrier bug in DMM driver - fix interrupt management in DMM driver - partial workaround for errata i878 - fix use of freed memory - some cleanups Signed-off-by:
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Dave Airlie authored
Merge tag 'drm-misc-next-fixes-2018-10-03' of git://anongit.freedesktop.org/drm/drm-misc into drm-next - Add EXPERT config option to allow phys mem leak from fbdev for blob drivers (Neil) Cc: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by:
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git://people.freedesktop.org/~thomash/linuxDave Airlie authored
Mostly code reorganizations and optimizations for vmwgfx. - Move TTM code that's only used by vmwgfx to vmwgfx - Break out the vmwgfx buffer- and resource validation code to a separate source file - Get rid of a number of atomic operations during command buffer validation. From: Thomas Hellstrom <thellstrom@vmware.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180928131157.2810-1-thellstrom@vmware.com
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- 03 Oct, 2018 1 commit
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Neil Armstrong authored
Since "drm/fb: Stop leaking physical address", the default behaviour of the DRM fbdev emulation is to set the smem_base to 0 and pass the new FBINFO_HIDE_SMEM_START flag. The main reason is to avoid leaking physical addresse to user-space, and it follows a general move over the kernel code to avoid user-space to manipulate physical addresses and then use some other mechanisms like dma-buf to transfer physical buffer handles over multiple subsystems. But, a lot of devices depends on closed sources binaries to enable OpenGL hardware acceleration that uses this smem_start value to pass physical addresses to out-of-tree modules in order to render into these physical adresses. These should use dma-buf buffers allocated from the DRM display device instead and stop relying on fbdev overallocation to gather DMA memory (some HW vendors delivers GBM and Wayland capable binaries, but older unsupported devices won't have these new binaries and are doomed until an Open Source solution like Lima finalizes). Since these devices heavily depends on this kind of software and because the smem_start population was available for years, it's a breakage to stop leaking smem_start without any alternative solutions. This patch adds a Kconfig depending on the EXPERT config and an unsafe kernel module parameter tainting the kernel when enabled. A clear comment and Kconfig help text was added to clarify why and when this patch should be reverted, but in the meantime it's a necessary feature to keep. Cc: Dave Airlie <airlied@gmail.com> Cc: Daniel Vetter <daniel.vetter@ffwll.ch> Cc: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com> Cc: Noralf Trønnes <noralf@tronnes.org> Cc: Maxime Ripard <maxime.ripard@bootlin.com> Cc: Eric Anholt <eric@anholt.net> Cc: Lucas Stach <l.stach@pengutronix.de> Cc: Rob Clark <robdclark@gmail.com> Cc: Ben Skeggs <skeggsb@gmail.com> Cc: Christian König <christian.koenig@amd.com> Signed-off-by:
Neil Armstrong <narmstrong@baylibre.com> Reviewed-by:
Maxime Ripard <maxime.ripard@bootlin.com> Tested-by:
Daniel Vetter <daniel.vetter@ffwll.ch> Acked-by:
Dave Airlie <airlied@gmail.com> Link: https://patchwork.freedesktop.org/patch/msgid/1538136355-15383-1-git-send-email-narmstrong@baylibre.com
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- 02 Oct, 2018 1 commit
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Ayan Kumar Halder authored
AFBC buffers include additional metadata which increases the required allocation size. Implement the appropriate size validation and sanity checking for AFBC buffers. Added malidp specific function for framebuffer creation. This checks if the framebuffer has AFBC modifiers and if so, it verifies the necessary constraints on the size, alignment, offsets and pitch. Changes from v2: - Replaced DRM_ERROR() with DRM_DEBUG_KMS() in malidp_verify_afbc_framebuffer_caps() and malidp_verify_afbc_framebuffer_size() Signed-off-by:
Ayan Kumar halder <ayan.halder@arm.com> Reviewed-by:
Brian Starkey <brian.starkey@arm.com> Reviewed-by:
Liviu Dudau <liviu.dudau@arm.com> Signed-off-by:
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