1. 26 Aug, 2015 34 commits
  2. 25 Aug, 2015 1 commit
  3. 14 Aug, 2015 5 commits
    • Jani Nikula's avatar
      drm/i915: remove excessive scaler debugging messages · 66e28066
      Jani Nikula authored
      There's so much scaler debugging messages that it makes other debugging
      hard. Remove them.
      Signed-off-by: default avatarJani Nikula <jani.nikula@intel.com>
      Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
      66e28066
    • Dave Gordon's avatar
      drm/i915: Debugfs interface for GuC submission statistics · 8b417c26
      Dave Gordon authored
      This provides a means of reading status and counts relating
      to GuC actions and submissions.
      
      v2:
          Remove surplus blank line in output [Chris Wilson]
      
      v5:
          Added GuC per-engine submission & seqno statistics
      
      v6:
          Add per-ring statistics to client, refactor client-dumper.
      Signed-off-by: default avatarDave Gordon <david.s.gordon@intel.com>
      Signed-off-by: default avatarAlex Dai <yu.dai@intel.com>
      Reviewed-by: default avatarTom O'Rourke <Tom.O'Rourke@intel.com>
      Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
      8b417c26
    • Alex Dai's avatar
      drm/i915: Integrate GuC-based command submission · d1675198
      Alex Dai authored
      GuC-based submission is mostly the same as execlist mode, up to
      intel_logical_ring_advance_and_submit(), where the context being
      dispatched would be added to the execlist queue; at this point
      we submit the context to the GuC backend instead.
      
      There are, however, a few other changes also required, notably:
      1.  Contexts must be pinned at GGTT addresses accessible by the GuC
          i.e. NOT in the range [0..WOPCM_SIZE), so we have to add the
          PIN_OFFSET_BIAS flag to the relevant GGTT-pinning calls.
      
      2.  The GuC's TLB must be invalidated after a context is pinned at
          a new GGTT address.
      
      3.  GuC firmware uses the one page before Ring Context as shared data.
          Therefore, whenever driver wants to get base address of LRC, we
          will offset one page for it. LRC_PPHWSP_PN is defined as the page
          number of LRCA.
      
      4.  In the work queue used to pass requests to the GuC, the GuC
          firmware requires the ring-tail-offset to be represented as an
          11-bit value, expressed in QWords. Therefore, the ringbuffer
          size must be reduced to the representable range (4 pages).
      
      v2:
          Defer adding #defines until needed [Chris Wilson]
          Rationalise type declarations [Chris Wilson]
      
      v4:
          Squashed kerneldoc patch into here [Daniel Vetter]
      
      v5:
          Update request->tail in code common to both GuC and execlist modes.
          Add a private version of lr_context_update(), as sharing the
              execlist version leads to race conditions when the CPU and
              the GuC both update TAIL in the context image.
          Conversion of error-captured HWS page to string must account
              for offset from start of object to actual HWS (LRC_PPHWSP_PN).
      
      Issue: VIZ-4884
      Signed-off-by: default avatarAlex Dai <yu.dai@intel.com>
      Signed-off-by: default avatarDave Gordon <david.s.gordon@intel.com>
      Reviewed-by: default avatarTom O'Rourke <Tom.O'Rourke@intel.com>
      Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
      d1675198
    • Dave Gordon's avatar
      drm/i915: Interrupt routing for GuC submission · 4df001d3
      Dave Gordon authored
      Turn on interrupt steering to route necessary interrupts to GuC.
      
      v6:
          Rebased
      
      Issue: VIZ-4884
      Signed-off-by: default avatarAlex Dai <yu.dai@intel.com>
      Signed-off-by: default avatarDave Gordon <david.s.gordon@intel.com>
      Reviewed-by: default avatarTom O'Rourke <Tom.O'Rourke@intel.com>
      Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
      4df001d3
    • Dave Gordon's avatar
      drm/i915: Implementation of GuC submission client · 44a28b1d
      Dave Gordon authored
      A GuC client has its own doorbell and workqueue. It maintains the
      doorbell cache line, process description object and work queue item.
      
      A default guc_client is created for the i915 driver to use for
      normal-priority in-order submission.
      
      Note that the created client is not yet ready for use; doorbell
      allocation will fail as we haven't yet linked the GuC's context
      descriptor to the default contexts for each ring (see later patch).
      
      v2:
          Defer adding structure members until needed [Chris Wilson]
          Rationalise type declarations [Chris Wilson]
      
      v5:
          Add GuC per-engine submission & seqno statistics.
          Move wq locking to encompass both get_space() and add_item().
          Take forcewake lock in host2guc_action() [Tom O'Rourke]
      
      v6:
          Fix GuC doorbell cacheline selection code (the
              cacheline-within-page calculation was wrong).
          Rename GuC priorities to make them closer to the names used in
              the GuC firmware source, matching what the autogenerated
              versions will (probably) be.
          Add per-ring statistics to client.
      
      Issue: VIZ-4884
      Signed-off-by: default avatarAlex Dai <yu.dai@intel.com>
      Signed-off-by: default avatarDave Gordon <david.s.gordon@intel.com>
      Reviewed-by: default avatarTom O'Rourke <Tom.O'Rourke@intel.com>
      Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
      44a28b1d