- 09 Oct, 2023 24 commits
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Boyuan Zhang authored
Update IB starting address alignment and size alignment with correct values for decode and encode IPs. Decode IB starting address alignment: 256 bytes Decode IB size alignment: 64 bytes Encode IB starting address alignment: 256 bytes Encode IB size alignment: 4 bytes Also bump amdgpu driver version for this update. Signed-off-by:
Boyuan Zhang <boyuan.zhang@amd.com> Reviewed-by:
Christian König <christian.koenig@amd.com> Acked-by:
Alex Deucher <alexander.deucher@amd.com> Signed-off-by:
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Gabe Teeger authored
[what] does_configuration_meet_sw_policies check was not done in the validate_only portion of dml2, so some unsupported modes were passing bw validation, only to fail the same check later in validate_and_build. now we add the check to validate_only. Also add line in dcn35_resource to ensure that value set for enable_windowed_mpo_odm gets passed to dml. [why] Immediate black screen during video playback at 4k144hz. The debugger showed that we were failing validation in dml on every updateplanes(). Reviewed-by:
Wenjing Liu <wenjing.liu@amd.com> Acked-by:
Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by:
Gabe Teeger <gabe.teeger@amd.com> Signed-off-by:
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Daniel Miess authored
Update DML2 with replay vblank logic found in DML1. Reviewed-by:
Charlene Liu <charlene.liu@amd.com> Acked-by:
Daniel Miess <daniel.miess@amd.com> Signed-off-by:
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Saaem Rizvi authored
[Why] There are certain cases during a transition to ODM that might cause corruption on the display. This occurs when we choose certain pipes in a particular state. [How] We now will store the pipe indexes of the any pipes that might be problematic to switch to during an ODM transition, and only use them as a last resort. Reviewed-by:
Dmytro Laktyushkin <dmytro.laktyushkin@amd.com> Acked-by:
Saaem Rizvi <syedsaaem.rizvi@amd.com> Signed-off-by:
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Charlene Liu authored
dc->dml2_options.use_native_pstate_optimization flag will make driver use dcn32 legacy_svp_drr related tuning. Set this to false fixed the stutter underflow issue also based on HW suggest disable ODM by default and let DML choose it. Reviewed-by:
Zhan Liu <zhan.liu@amd.com> Acked-by:
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Sung Joon Kim authored
[why] Surface height/width for Chroma has another variable that it should be intialized to, chroma_size. Fixing this will help pass DML2.0 validation for YCbCr420 tests, DCHB006.109,129, DCHB014.011,012. [how] Assign SurfaceHeight/WidthC to chroma_size.height/width Reviewed-by:
Sung Joon Kim <sungkim@amd.com> Signed-off-by:
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Taimur Hassan authored
Rework dml2_map_dc_pipes to keep the logic clean. Reviewed-by:
Chaitanya Dhere <chaitanya.dhere@amd.com> Acked-by:
Taimur Hassan <syed.hassan@amd.com> Signed-off-by:
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Taimur Hassan authored
[Why & How] DML2 did not carry over DML1 logic that splits pipe for stero timings. Pipe splitting is needed in this case to pass stereo tests. Reviewed-by:
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Sung Joon Kim authored
[why] Regression from DML1.0 where we use differen DET buffer sizes for each pipe. From the spec, we need to use DET buffer size of 384 kb for each pipe [how] Ensure to use 384 kb DET buffer sizes for each available pipe. Reviewed-by:
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Sung Joon Kim authored
[why] There are cases where more than 1 stream can be mapped to the same surface. DML2.0 does not seem to handle these cases. [how] Make sure to account for the stream id when deriving the plane id. By doing this, each plane id will be unique based on the stream id. Reviewed-by:
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Charlene Liu authored
Add z8 watermarks to struct for later ASIC use. Reviewed-by:
Alvin Lee <alvin.lee2@amd.com> Acked-by:
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Qingqing Zhuo authored
Enable DML2 for DCN35. Changes since V1: - Remove hard coded values Acked-by:
Harry Wentland <Harry.Wentland@amd.com> Signed-off-by:
Roman Li <roman.li@amd.com> Signed-off-by:
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Qingqing Zhuo authored
DC is transitioning from DML to DML2, and this commit introduces all the required changes for some of the already available ASICs and adds the required code infra to support new ASICs under DML2. DML2 is also a generated code that provides better mode verification and programming models for software/hardware, and it enables a better way to create validation tools. This version is more like a middle step to the complete transition to the DML2 version. Changes since V1: - Alex: Fix typos Changes since V2: - Update DC includes Changes since V3: - Fix 32 bit compilation issues on x86 Changes since V4: - Avoid compilation of DML2 on some not supported 32-bit architecture - Update commit message Co-developed-by:
Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by:
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Rodrigo Siqueira authored
For some reason, the dml code is not guarded under CONFIG_DRM_AMD_DC_FP in the Makefile. This commit moves the dml code under the DC_FP guard. Reviewed-by:
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Rodrigo Siqueira authored
bw_fixed does not need any FPU operation, and it is used on DCE and DCN. For this reason, this commit moves bw_fixed to the basic folder outside DML. Reviewed-by:
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Rodrigo Siqueira authored
The custom_float file does not have any FPU operation, so it should be inside DML. This commit moves the file to the basic folder. Reviewed-by:
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Rodrigo Siqueira authored
dce_calcs does not have FPU operations, and it is required for DCE and DCN. Remove this file from the DML folder and add it to the basic folder visible for DCE and DCN. Reviewed-by:
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Alex Deucher authored
When ROCm is active enable additional SMU 13.0.0 optimizations. This reuses the unused powersave profile on PMFW. v2: move to the swsmu code since we need both bits active in the workload mask. Reviewed-by:Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
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Sebastian Andrzej Siewior authored
dcn20_validate_bandwidth_fp() is invoked while FPU access has been enabled. FPU access requires disabling preemption even on PREEMPT_RT. It is not possible to allocate memory with disabled preemption even with GFP_ATOMIC on PREEMPT_RT. Move the memory allocation before FPU access is enabled. To preserve previous "clean" state of "pipes" add a memset() before the second invocation of dcn20_validate_bandwidth_internal() where the variable is used. Acked-by:
Sebastian Andrzej Siewior <bigeasy@linutronix.de> Signed-off-by:
Hamza Mahfooz <hamza.mahfooz@amd.com> Signed-off-by:
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Sebastian Andrzej Siewior authored
dcn21_validate_bandwidth_fp() is invoked while FPU access has been enabled. FPU access requires disabling preemption even on PREEMPT_RT. It is not possible to allocate memory with disabled preemption even with GFP_ATOMIC on PREEMPT_RT. Move the memory allocation before FPU access is enabled. Link: https://bugzilla.kernel.org/show_bug.cgi?id=217928Acked-by:
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Sebastian Andrzej Siewior authored
Add a warning if the FPU is used from any context other than task context. This is only precaution since the code is not able to be used from softirq while the API allows it on x86 for instance. Acked-by:
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Mario Limonciello authored
For pptable structs that use flexible array sizes, use flexible arrays. Link: https://bugs.launchpad.net/ubuntu/+source/linux/+bug/2036742Signed-off-by:
Mario Limonciello <mario.limonciello@amd.com> Acked-by:
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Mario Limonciello authored
For pptable structs that use flexible array sizes, use flexible arrays. Suggested-by:
Felix Held <felix.held@amd.com> Link: https://gitlab.freedesktop.org/drm/amd/-/issues/2894Signed-off-by:
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Mario Limonciello authored
For pptable structs that use flexible array sizes, use flexible arrays. Suggested-by:
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- 05 Oct, 2023 16 commits
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Kees Cook authored
Prepare for the coming implementation by GCC and Clang of the __counted_by attribute. Flexible array members annotated with __counted_by can have their accesses bounds-checked at run-time via CONFIG_UBSAN_BOUNDS (for array indexing) and CONFIG_FORTIFY_SOURCE (for strcpy/memcpy-family functions). As found with Coccinelle[1], add __counted_by for struct amdgpu_bo_list. Additionally, since the element count member must be set before accessing the annotated flexible array member, move its initialization earlier. Cc: Alex Deucher <alexander.deucher@amd.com> Cc: "Christian König" <christian.koenig@amd.com> Cc: "Pan, Xinhui" <Xinhui.Pan@amd.com> Cc: David Airlie <airlied@gmail.com> Cc: Daniel Vetter <daniel@ffwll.ch> Cc: "Gustavo A. R. Silva" <gustavoars@kernel.org> Cc: Luben Tuikov <luben.tuikov@amd.com> Cc: Christophe JAILLET <christophe.jaillet@wanadoo.fr> Cc: Felix Kuehling <Felix.Kuehling@amd.com> Cc: amd-gfx@lists.freedesktop.org Cc: dri-devel@lists.freedesktop.org Cc: linux-hardening@vger.kernel.org Link: https://github.com/kees/kernel-tools/blob/trunk/coccinelle/examples/counted_by.cocci [1] Reviewed-by:
Luben Tuikov <luben.tuikov@amd.com> Reviewed-by:
Kees Cook <keescook@chromium.org> Signed-off-by:
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Srinivasan Shanmugam authored
There is no reason to call return at the end of function that returns void. Fixes the below: WARNING: void function return statements are not generally useful Thus remove such a statement in the affected functions. Cc: Christian König <christian.koenig@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: "Pan, Xinhui" <Xinhui.Pan@amd.com> Signed-off-by:
Srinivasan Shanmugam <srinivasan.shanmugam@amd.com> Reviewed-by:
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Lijo Lazar authored
Add documentation for board info sysfs attribute. Signed-off-by:
Lijo Lazar <lijo.lazar@amd.com> Reviewed-by:
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Lijo Lazar authored
Add a sysfs attribute which shows the board form factor like OAM or CEM. Signed-off-by:
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Lijo Lazar authored
Add support to query package types supported in smuio v13.0 ASICs. Signed-off-by:
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Lijo Lazar authored
Expand support to get other board types like OAM or CEM. Signed-off-by:
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Sathishkumar S authored
fix wrong ip count INFO on spatial partitions. update the query to return the instance count corresponding to the partition id. v2: initialize variables only when required to be (Christian) move variable declarations to the beginning of function (Christian) Signed-off-by:
Sathishkumar S <sathishkumar.sundararaju@amd.com> Acked-by:
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Asad Kamal authored
Remove set df cstate as disallow df state is not required for SMUv13.0.6 Signed-off-by:
Asad Kamal <asad.kamal@amd.com> Reviewed-by:
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Lijo Lazar authored
Move definition of package type to amdgpu_smuio header and add new package types for CEM and OAM. Signed-off-by:
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Srinivasan Shanmugam authored
Fixes the below: ERROR: Macros with complex values should be enclosed in parentheses WARNING: macros should not use a trailing semicolon +#define amdgpu_inc_vram_lost(adev) atomic_inc(&((adev)->vram_lost_counter)); Cc: Christian König <christian.koenig@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: "Pan, Xinhui" <Xinhui.Pan@amd.com> Signed-off-by:
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Xiaogang Chen authored
This patch implements partial migration in gpu page fault according to migration granularity(default 2MB) and not split svm range in cpu page fault handling. A svm range may include pages from both system ram and vram of one gpu now. These chagnes are expected to improve migration performance and reduce mmu callback and TLB flush workloads. Signed-off-by:
Xiaogang Chen <xiaogang.chen@amd.com> Reviewed-by:
Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by:
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Sebastian Andrzej Siewior authored
The fpu_recursion_depth counter is used to ensure that dc_fpu_begin() can be invoked multiple times while the FPU-disable function itself is only invoked once. Also the counter part (dc_fpu_end()) is ballanced properly. Instead of using the get_cpu_ptr() dance around the inc it is simpler to increment the per-CPU variable directly. Also the per-CPU variable has to be incremented and decremented on the same CPU. This is ensured by the inner-part which disables preemption. This is kind of not obvious, works and the preempt-counter is touched a few times for no reason. Disable preemption before incrementing fpu_recursion_depth for the first time. Keep preemption disabled until dc_fpu_end() where the counter is decremented making it obvious that the preemption has to stay disabled while the counter is non-zero. Use simple inc/dec functions. Remove the nested preempt_disable/enable functions which are now not needed. Acked-by:
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Sebastian Andrzej Siewior authored
This is a revert of the commit mentioned below while it is not wrong, as in the kernel will explode, having migrate_disable() here it is complete waste of resources. Additionally commit message is plain wrong the review tag does not make it any better. The migrate_disable() interface has a fat comment describing it and it includes the word "undesired" in the headline which should tickle people to read it before using it. Initially I assumed it is worded too harsh but now I beg to differ. The reviewer of the original commit, even not understanding what migrate_disable() does should ask the following: - migrate_disable() is added only to the CONFIG_X86 block and it claims to protect fpu_recursion_depth. Why are the other the architectures excluded? - migrate_disable() is added after fpu_recursion_depth was modified. Shouldn't it be added before the modification or referencing takes place? Moving on. Disabling preemption DOES prevent CPU migration. A task, that can not be pushed away from the CPU by the scheduler (due to disabled preemption) can not be pushed or migrated to another CPU. Disabling migration DOES NOT ensure consistency of per-CPU variables. It only ensures that the task acts always on the same per-CPU variable. The task remains preemptible meaning multiple tasks can access the same per-CPU variable. This in turn leads to inconsistency for the statement *pcpu -= 1; with two tasks on one CPU and a preemption point during the RMW operation: Task A Task B read pcpu to reg # 0 inc reg # 0 -> 1 read pcpu to reg # 0 inc reg # 0 -> 1 write reg to pcpu # 1 write reg to pcpu # 1 At the end pcpu reads 1 but should read 2 instead. Boom. get_cpu_ptr() already contains a preempt_disable() statement. That means that the per-CPU variable can only be referenced by a single task which is currently running. The only inconsistency that can occur if the variable is additionally accessed from an interrupt. Remove migrate_disable/enable() from dc_fpu_begin/end(). Cc: Tianci Yin <tianci.yin@amd.com> Cc: Aurabindo Pillai <aurabindo.pillai@amd.com> Fixes: 0c316556 ("drm/amd/display: Disable migration to ensure consistency of per-CPU variable") Acked-by: -
Randy Dunlap authored
Correct typos of "occurred". Signed-off-by:
Randy Dunlap <rdunlap@infradead.org> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: Christian König <christian.koenig@amd.com> Cc: "Pan, Xinhui" <Xinhui.Pan@amd.com> Cc: amd-gfx@lists.freedesktop.org Reviewed-by:
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Alex Deucher authored
Don't update the fault cache if status is 0. In the multiple fault case, subsequent faults will return a 0 status which is useless for userspace and replaces the useful fault status, so only update if status is non-0. Reviewed-by:
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Alex Deucher authored
Add a interface to query the last GPU page fault for the process. Useful for debugging context lost errors. v2: split vmhub representation between kernel and userspace v3: add locking when fetching fault info in INFO IOCTL Mesa MR: https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23238 libdrm MR: https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23238 Cc: samuel.pitoiset@gmail.com Reviewed-by:
Guchun Chen <guchun.chen@amd.com> Signed-off-by:
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