- 10 Feb, 2023 2 commits
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William Zhang authored
For SPI controller that implements transfer_one_message, it needs to insert the delay that required by cs change event between the transfers. Add a wrapper for the local function _spi_transfer_cs_change_delay_exec and export it for SPI controller driver to use. Signed-off-by:
William Zhang <william.zhang@broadcom.com> Link: https://lore.kernel.org/r/20230209200246.141520-9-william.zhang@broadcom.comSigned-off-by:
Mark Brown <broonie@kernel.org>
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Mauro Lima authored
Modern intel hardware uses controllers that work in hardware sequencing mode. In this mode, the controller exposes a subset of operations, like read, write and erase, making it easier and less error-prone for use. On the other hand, most of the controllers handled by the platform driver use software sequencing that exposes the entire set of operations i.e. exposes the low level SPI-NOR opcodes to the software for use. Update PCI and Platform help text with this information. Signed-off-by:
Mauro Lima <mauro.lima@eclypsium.com> Acked-by:
Mika Westerberg <mika.westerberg@linux.intel.com> Link: https://lore.kernel.org/r/20230210164158.211065-1-mauro.lima@eclypsium.comSigned-off-by:
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- 09 Feb, 2023 11 commits
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Mark Brown authored
Merge series from Xiangsheng Hou <xiangsheng.hou@mediatek.com>: This patch series split from bellow series which pick-up spi relevant patches https://lore.kernel.org/all/20230130030656.12127-1-xiangsheng.hou@mediatek.com. This series add MediaTek MT7986 SPI NAND controller support, add read latch latency, smaple delay adjust and add optional nfi_hclk.
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Xiangsheng Hou authored
Add mediatek,rx-latch-latency-ns property which adjust data read latch latency in the unit of nanoseconds. Signed-off-by:
Xiangsheng Hou <xiangsheng.hou@mediatek.com> Acked-by:
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by:
AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20230201020921.26712-6-xiangsheng.hou@mediatek.comSigned-off-by:
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Xiangsheng Hou authored
Add dt-bindings documentation of SPI NAND controller for MediaTek MT7986 SoC platform. And add optional nfi_hclk property which is needed for MT7986. Signed-off-by:
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Xiangsheng Hou authored
Add snfi sample delay and read latency adjustment which can get from dts property. Signed-off-by:
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Xiangsheng Hou authored
Add optional nfi_hclk which is needed for MT7986. Signed-off-by:
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Xiangsheng Hou authored
Change default page format to setup default setting since the sector size 1024 on MT7986 will lead to probe fail. Signed-off-by:
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William Zhang authored
Polling mode provides better throughput in general by avoiding the interrupt overhead as the maximum data size one interrupt can handle is only 512 bytes. So switch to polling mode as the default mode but add a driver sysfs option wait_mode to allow user manually changing the mode at run time between interrupt and polling. Also add driver banner message when the driver is loaded successfully. When test on a Broadcom BCM47622(ARM A7 dual core) reference board with WINBOND W25N01GV SPI NAND chip at 100MHz SPI clock using the MTD speed test suite, it shows about 15% improvement on the write and 30% on the read: ** Interrupt mode ** mtd_speedtest: MTD device: 0 count: 16 mtd_speedtest: MTD device size 134217728, eraseblock size 131072, page size 2048, count of eraseblocks 1024, pages per eraseblock 64, OOB size 64 mtd_test: scanning for bad eraseblocks mtd_test: scanned 16 eraseblocks, 0 are bad mtd_speedtest: testing eraseblock write speed mtd_speedtest: eraseblock write speed is 3072 KiB/s mtd_speedtest: testing eraseblock read speed mtd_speedtest: eraseblock read speed is 6690 KiB/s mtd_speedtest: testing page write speed mtd_speedtest: page write speed is 3066 KiB/s mtd_speedtest: testing page read speed mtd_speedtest: page read speed is 6762 KiB/s mtd_speedtest: testing 2 page write speed mtd_speedtest: 2 page write speed is 3071 KiB/s mtd_speedtest: testing 2 page read speed mtd_speedtest: 2 page read speed is 6772 KiB/s ** Polling mode ** mtd_speedtest: MTD device: 0 count: 16 mtd_speedtest: MTD device size 134217728, eraseblock size 131072, page size 2048, count of eraseblocks 1024, pages per eraseblock 64, OOB size 64 mtd_test: scanning for bad eraseblocks mtd_test: scanned 16 eraseblocks, 0 are bad mtd_speedtest: testing eraseblock write speed mtd_speedtest: eraseblock write speed is 3542 KiB/s mtd_speedtest: testing eraseblock read speed mtd_speedtest: eraseblock read speed is 8825 KiB/s mtd_speedtest: testing page write speed mtd_speedtest: page write speed is 3563 KiB/s mtd_speedtest: testing page read speed mtd_speedtest: page read speed is 8787 KiB/s mtd_speedtest: testing 2 page write speed mtd_speedtest: 2 page write speed is 3572 KiB/s mtd_speedtest: testing 2 page read speed mtd_speedtest: 2 page read speed is 8806 KiB/s Signed-off-by:
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William Zhang authored
HSSPI controller uses big endian for the opcode in the message to the controller ping pong buffer. Use cpu_to_be16 to properly handle the endianness for both big and little endian host. Fixes: 142168eb ("spi: bcm63xx-hsspi: add bcm63xx HSSPI driver") Signed-off-by:
Kursad Oney <kursad.oney@broadcom.com> Signed-off-by:
Florian Fainelli <f.fainelli@gmail.com> Link: https://lore.kernel.org/r/20230207065826.285013-7-william.zhang@broadcom.comSigned-off-by:
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William Zhang authored
New compatible string brcm,bcmbca-hsspi-v1.0 is introduced based on dts document brcm,bcm63xx-hsspi.yaml. Add it to the driver to support this new binding. Signed-off-by:
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William Zhang authored
The new Broadcom Broadband BCMBCA SoCs includes a updated HSSPI controller. Add new compatible strings to differentiate the old and new controller while keeping MIPS based chip with the old compatible. Update property requirements for these two revisions of the controller. Also add myself and Kursad as the maintainers. Signed-off-by:
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William Zhang authored
This is the preparation for updates on the bcm63xx hsspi driver. Convert the text based bindings to json-schema per new dts requirement. Signed-off-by:
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- 07 Feb, 2023 1 commit
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Mauro Lima authored
Modern CPUs exposes this controller as PCI device that only uses hardware sequencing capabilities which is safer than software sequencing. Leave the platform driver as *DANGEROUS* and update help text since most of these controllers are using software sequencing. Signed-off-by:
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- 06 Feb, 2023 2 commits
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Dan Carpenter authored
This unlocks twice due to a merge issue. Fixes: 35bba23e ("Merge remote-tracking branch 'spi/for-6.2' into spi-6.2") Signed-off-by:
Dan Carpenter <error27@gmail.com> Link: https://lore.kernel.org/r/Y+ETCk7XKfAy8yWQ@kiliSigned-off-by:
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Mark Brown authored
The automated merge for the spidev locking fixes is going wrong and merging the unlock twice.
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- 02 Feb, 2023 2 commits
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Mauro Lima authored
Add Device IDs to the module table for the following controllers: - 9da4 Cannon Lake 300 Series On-Package - a2a4 200 Series/Z370 Chipset Family SPI Controller - 9d24 Intel
® 200 Series Chipset Family (Including Intel® X299), Intel® Z370 Intel® H310C,B365, also Intel® B460 and H410 Chipset Platform Controller Hub Signed-off-by: -
Mauro Lima authored
Some private data fields have to change from bxt_info to cnl_info. Here is the list of Device IDs with the respective documentation taken for validation: 0xa0a4 - Intel® 500 Series Chipset Family On-Package PCH 0x02a4 - Intel® 400 Series Chipset Family On-Package PCH 0x06a4 - Intel® 400 Series Chipset Family Platform Controller Hub 0x34a4 - Intel® 495 Chipset Family On-Package 0xa3a4 - Intel® B460 and H410 Chipset According to documentation Broxton controller type has five PR registers. Signed-off-by:
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- 01 Feb, 2023 2 commits
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Mark Brown authored
Merge series from Amit Kumar Mahapatra <amit.kumar-mahapatra@amd.com>: In preparation for supporting devices with multiple chip selects add an interface for accessing the chip selects via a function.
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Amit Kumar Mahapatra authored
Supporting multi-cs in spi core and spi controller drivers would require the chip_select & cs_gpiod members of struct spi_device to be an array. But changing the type of these members to array would break the spi driver functionality. To make the transition smoother introduced four new APIs to get/set the spi->chip_select & spi->cs_gpiod and replaced all spi->chip_select and spi->cs_gpiod references in spi core with the API calls. While adding multi-cs support in further patches the chip_select & cs_gpiod members of the spi_device structure would be converted to arrays & the "idx" parameter of the APIs would be used as array index i.e., spi->chip_select[idx] & spi->cs_gpiod[idx] respectively. Suggested-by:
Lars-Peter Clausen <lars@metafoo.de> Signed-off-by:
Amit Kumar Mahapatra <amit.kumar-mahapatra@amd.com> Reviewed-by:
Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/20230119185342.2093323-2-amit.kumar-mahapatra@amd.comSigned-off-by:
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- 30 Jan, 2023 2 commits
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Arnd Bergmann authored
Selecting a symbol with additional dependencies requires adding the same dependency here: WARNING: unmet direct dependencies detected for MUX_MMIO Depends on [n]: MULTIPLEXER [=y] && OF [=n] Selected by [y]: - SPI_DW_BT1 [=y] && SPI [=y] && SPI_MASTER [=y] && SPI_DESIGNWARE [=y] && (MIPS_BAIKAL_T1 || COMPILE_TEST [=y]) Drop the 'select' here to avoid the problem. Anyone using the dw-bt1 SPI driver should make sure they include the mux driver as well now. Fixes: 72188381 ("spi: dw-bt1: Fix undefined devm_mux_control_get symbol") Fixes: abf00907 ("spi: dw: Add Baikal-T1 SPI Controller glue driver") Link: https://lore.kernel.org/all/20221218192523.c6vnfo26ua6xqf26@mobilestation/Signed-off-by:
Arnd Bergmann <arnd@arndb.de> Reviewed-by:
Serge Semin <fancer.lancer@gmail.com> Link: https://lore.kernel.org/r/20230130140156.3620863-1-arnd@kernel.orgSigned-off-by:
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Mark Brown authored
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- 27 Jan, 2023 3 commits
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Bartosz Golaszewski authored
When calling spidev_message() from the one of the ioctl() callbacks, the spi_lock is already taken. When we then end up calling spidev_sync(), we get the following splat: [ 214.047619] [ 214.049198] ============================================ [ 214.054533] WARNING: possible recursive locking detected [ 214.059858] 6.2.0-rc3-0.0.0-devel+git.97ec4d55 #1 Not tainted [ 214.065969] -------------------------------------------- [ 214.071290] spidev_test/1454 is trying to acquire lock: [ 214.076530] c4925dbc (&spidev->spi_lock){+.+.}-{3:3}, at: spidev_ioctl+0x8e0/0xab8 [ 214.084164] [ 214.084164] but task is already holding lock: [ 214.090007] c4925dbc (&spidev->spi_lock){+.+.}-{3:3}, at: spidev_ioctl+0x44/0xab8 [ 214.097537] [ 214.097537] other info that might help us debug this: [ 214.104075] Possible unsafe locking scenario: [ 214.104075] [ 214.110004] CPU0 [ 214.112461] ---- [ 214.114916] lock(&spidev->spi_lock); [ 214.118687] lock(&spidev->spi_lock); [ 214.122457] [ 214.122457] *** DEADLOCK *** [ 214.122457] [ 214.128386] May be due to missing lock nesting notation [ 214.128386] [ 214.135183] 2 locks held by spidev_test/1454: [ 214.139553] #0: c4925dbc (&spidev->spi_lock){+.+.}-{3:3}, at: spidev_ioctl+0x44/0xab8 [ 214.147524] #1: c4925e14 (&spidev->buf_lock){+.+.}-{3:3}, at: spidev_ioctl+0x70/0xab8 [ 214.155493] [ 214.155493] stack backtrace: [ 214.159861] CPU: 0 PID: 1454 Comm: spidev_test Not tainted 6.2.0-rc3-0.0.0-devel+git.97ec4d55 #1 [ 214.169012] Hardware name: Freescale i.MX6 Quad/DualLite (Device Tree) [ 214.175555] unwind_backtrace from show_stack+0x10/0x14 [ 214.180819] show_stack from dump_stack_lvl+0x60/0x90 [ 214.185900] dump_stack_lvl from __lock_acquire+0x874/0x2858 [ 214.191584] __lock_acquire from lock_acquire+0xfc/0x378 [ 214.196918] lock_acquire from __mutex_lock+0x9c/0x8a8 [ 214.202083] __mutex_lock from mutex_lock_nested+0x1c/0x24 [ 214.207597] mutex_lock_nested from spidev_ioctl+0x8e0/0xab8 [ 214.213284] spidev_ioctl from sys_ioctl+0x4d0/0xe2c [ 214.218277] sys_ioctl from ret_fast_syscall+0x0/0x1c [ 214.223351] Exception stack(0xe75cdfa8 to 0xe75cdff0) [ 214.228422] dfa0: 00000000 00001000 00000003 40206b00 bee266e8 bee266e0 [ 214.236617] dfc0: 00000000 00001000 006a71a0 00000036 004c0040 004bfd18 00000000 00000003 [ 214.244809] dfe0: 00000036 bee266c8 b6f16dc5 b6e8e5f6 Fix it by introducing an unlocked variant of spidev_sync() and calling it from spidev_message() while other users who don't check the spidev->spi's existence keep on using the locking flavor. Reported-by:
Francesco Dolcini <francesco@dolcini.it> Fixes: 1f4d2dd4 ("spi: spidev: fix a race condition when accessing spidev->spi") Signed-off-by:
Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Tested-by:
Max Krummenacher <max.krummenacher@toradex.com> Link: https://lore.kernel.org/r/20230116144149.305560-1-brgl@bgdev.plSigned-off-by:
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Serge Semin authored
Due to using the u16 type in the min_t() macros the SPI transfer length will be cast to word before participating in the conditional statement implied by the macro. Thus if the transfer length is greater than 64KB the Tx/Rx FIFO threshold level value will be determined by the leftover of the truncated after the type-case length. In the worst case it will cause the dramatical performance drop due to the "Tx FIFO Empty" or "Rx FIFO Full" interrupts triggered on each xfer word sent/received to/from the bus. The problem can be easily fixed by specifying the unsigned int type in the min_t() macros thus preventing the possible data loss. Fixes: ea11370f ("spi: dw: get TX level without an additional variable") Reported-by:
Sergey Nazarov <Sergey.Nazarov@baikalelectronics.ru> Signed-off-by:
Serge Semin <Sergey.Semin@baikalelectronics.ru> Reviewed-by:
Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/r/20230113185942.2516-1-Sergey.Semin@baikalelectronics.ruSigned-off-by:
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Randy Dunlap authored
Correct spelling problems for Documentation/spi/ as reported by codespell. Signed-off-by:
Randy Dunlap <rdunlap@infradead.org> Link: https://lore.kernel.org/r/20230127064005.1558-28-rdunlap@infradead.orgSigned-off-by:
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- 25 Jan, 2023 3 commits
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Randy Dunlap authored
Correct a spelling mistake (reported by codespell). Also hyphenate "8-bit". Signed-off-by:
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Krzysztof Kozlowski authored
Cleanup examples: - use 4-space indentation (for cases when it is neither 4 not 2 space), - drop redundant blank lines, - use lowercase hex. No functional impact except adjusting to preferred coding style. Signed-off-by:
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Krzysztof Kozlowski authored
Cleanup by removing unneeded quotes from refs and redundant blank lines. No functional impact except adjusting to preferred coding style. Signed-off-by:
Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20230124083342.34869-1-krzysztof.kozlowski@linaro.orgSigned-off-by:
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- 23 Jan, 2023 5 commits
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Mark Brown authored
Merge series from Yang Yingliang <yangyingliang@huawei.com>: After introducing devm_spi_alloc_host/spi_alloc_host(), the legacy named function devm_spi_alloc_master/spi_alloc_master() can be replaced. And also change other legacy name master/slave to modern name host/target or controller.
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Krzysztof Kozlowski authored
Document existing SPI dev compatibles. Cc: Mark Brown <broonie@kernel.org> Signed-off-by:
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Yang Yingliang authored
Change legacy name master to modern name host or controller. No functional changed. Signed-off-by:
Yang Yingliang <yangyingliang@huawei.com> Link: https://lore.kernel.org/r/20230110131805.2827248-4-yangyingliang@huawei.comSigned-off-by:
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Yang Yingliang authored
Change legacy name master to modern name host or controller. No functional changed. Signed-off-by:
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Yang Yingliang authored
Change legacy name master to modern name host or controller. No functional changed. Signed-off-by:
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- 20 Jan, 2023 1 commit
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Krzysztof Kozlowski authored
Bring some order to reduce possibilities of conflicts. Signed-off-by:
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- 13 Jan, 2023 4 commits
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Mark Brown authored
Merge series from Hector Martin <marcan@marcan.st>: Commits f6c911f3 ("spi: dt-bindings: Introduce spi-cs-setup-ns property") and 33a2fde5 ("spi: Introduce spi-cs-setup-ns property") introduced a new property to represent the CS setup delay in the device tree, but they have some issues: - The property is only parsed as a 16-bit integer number of nanoseconds, which limits the maximum value to ~65us. This is not a reasonable upper limit, as some devices might need a lot more. - The property name is inconsistent with other delay properties, which use a "*-delay-ns" naming scheme. - Only the setup delay is introduced, but not the related hold and inactive delay times. This series fixes the issues and adds support for the two missing properties. Please pull in the first 3 patches as fixes for 6.2, to avoid introducing a problematic DT API in this release. The last two patches can wait until 6.3, though are probably harmless to throw in as fixes too, since they're trivial.
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Janne Grunau authored
Now that we support parsing the setup time from the Device Tree, we can also easily support the remaining hold and inactive time delay values. Signed-off-by:
Janne Grunau <j@jannau.net> Signed-off-by:
Hector Martin <marcan@marcan.st> Link: https://lore.kernel.org/r/20230113102309.18308-4-marcan@marcan.stSigned-off-by:
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Janne Grunau authored
These two properties complete the bindings for the Linux spi_device cs model, which includes cs_setup, cs_hold and cs_inactive delay values. Signed-off-by:
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Janne Grunau authored
65us is not a reasonable maximum for this property, as some devices might need a much longer setup time (e.g. those driven by firmware on the other end). Plus, device tree property values are in 32-bit cells and smaller widths should not be used without good reason. Also move the logic to a helper function, since this will later be used to parse other CS delay properties too. Fixes: 33a2fde5 ("spi: Introduce spi-cs-setup-ns property") Signed-off-by:
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- 11 Jan, 2023 2 commits
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Geert Uytterhoeven authored
Remove trailing whitespace that hurts my eyes. Signed-off-by:
Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/7c1b2700f3727e94600f5f7e10beef16f8dc64ed.1673425053.git.geert+renesas@glider.beSigned-off-by:
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Mark Brown authored
The newly added spi-cs-setup-ns doesn't really fit with the existing property names for delays, rename it so that it does before it makes it into a release and becomes ABI.
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