- 02 Sep, 2024 9 commits
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Dillon Varone authored
This reverts commit f0b7dcf2. It is causing graphics hangs. Reviewed-by:
Martin Leung <martin.leung@amd.com> Signed-off-by:
Dillon Varone <Dillon.Varone@amd.com> Signed-off-by:
Hamza Mahfooz <hamza.mahfooz@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Samson Tam authored
[Why] Certain profiles have higher HDR multiplier than SDR boost max which is not currently supported [How] Disable sharpness for these profiles Fixes: 1b0ce903 ("drm/amd/display: add improvements for text display and HDR DWM and MPO") Reviewed-by:
Samson Tam <Samson.Tam@amd.com> Signed-off-by:
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Meenakshikumar Somasundaram authored
[Why] To provide option to dpia control power management [How] By adding disable_usb4_pm_support bit field in dpia_debug option to control dpia power management Reviewed-by:
Jun Lei <jun.lei@amd.com> Signed-off-by:
Meenakshikumar Somasundaram <meenakshikumar.somasundaram@amd.com> Signed-off-by:
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Alex Deucher authored
Add ring reset callbacks for gfx and compute. Acked-by:
Vitaly Prosyak <vitaly.prosyak@amd.com> Signed-off-by:
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Samson Tam authored
[Why] Previous disable ODM policy due to underflow issue with sharpener. Issue is resolved after updating sharpening policy to apply to both windowed and fullscreen video [How] Remove sharpness check disabling Dynamic ODM policy Reviewed-by:
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Leo Li authored
Backlight updates require aux and/or register access. Therefore, driver needs to disallow IPS beforehand. So, acquire the dc lock before calling into dc to update backlight - we should be doing this regardless of IPS. Then, while the lock is held, disallow IPS before calling into dc, then allow IPS afterwards (if it was previously allowed). Reviewed-by:
Aurabindo Pillai <aurabindo.pillai@amd.com> Reviewed-by:
Roman Li <roman.li@amd.com> Signed-off-by:
Leo Li <sunpeng.li@amd.com> Signed-off-by:
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Daniel Sa authored
[Why] Some asserts are always hit on startup/Pnp when they should only be used to indicate when something has gone wrong. [How] Ignore result of getting function from bios cmd table for newer asics. Reviewed-by:
Daniel Sa <Daniel.Sa@amd.com> Signed-off-by:
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Nicholas Susanto authored
[Why] Setting min dispclk to 50Mhz outside clock lowering function causes unnecessary calls to SMU to lower dispclk and causes dentist hangs when there is no stream on the pipes. [How] Move the set minimum dispclk logic inside the lowering dispclk if statement. Fixes: 23444132 ("DCN35 set min dispclk to 50Mhz") Reviewed-by:
Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by:
Nicholas Susanto <Nicholas.Susanto@amd.com> Signed-off-by:
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Prike Liang authored
Implement the compute pipe reset, and the driver will fallback to pipe reset when queue reset fails. The pipe reset only deactivates the queue which is scheduled in the pipe, and meanwhile the MEC pipe will be reset to the firmware _start pointer. So, it seems pipe reset will cost more cycles than the queue reset; therefore, the driver tries to recover by doing queue reset first. Reviewed-by:
Lijo Lazar <lijo.lazar@amd.com> Signed-off-by:
Prike Liang <Prike.Liang@amd.com> Signed-off-by:
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- 29 Aug, 2024 13 commits
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Alex Deucher authored
This adds allocation latency, but aligns better with user expectations. The latency should improve with the drm buddy clearing patches that Arun has been working on. In addition this fixes the high CPU spikes seen when doing wipe on release. v2: always set AMDGPU_GEM_CREATE_VRAM_CLEARED (Christian) Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/3528 Fixes: a68c7eaa ("drm/amdgpu: Enable clear page functionality") Acked-by:
Arunpravin Paneer Selvam <Arunpravin.PaneerSelvam@amd.com> Reviewed-by: Michel Dänzer <mdaenzer@redhat.com> (v1) Signed-off-by:
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Jack Xiao authored
For mes11 old firmware has issue to map legacy queue, add a flag to switch mes to map legacy queue. Fixes: f9d8c5c7 ("drm/amdgpu/gfx: enable mes to map legacy queue support") Reported-by:
Andrew Worsley <amworsley@gmail.com> Link: https://lists.freedesktop.org/archives/amd-gfx/2024-August/112773.htmlSigned-off-by:
Jack Xiao <Jack.Xiao@amd.com> Reviewed-by:
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Yifan Zhang authored
ih1 is not initialized for APUs. Don't drain it or NULL pointer error will be triggered. Fixes: 6ef29715 ("drm/amdkfd: Change kfd/svm page fault drain handling") Signed-off-by:
Yifan Zhang <yifan1.zhang@amd.com> Reviewed-by:
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Alex Deucher authored
When MES is enabled KIQ is not available. Return an error when someone uses the debugfs preempt test interface in that case. Acked-by:
Srinivasan Shanmugam <srinivasan.shanmugam@amd.com> Signed-off-by:
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Alex Deucher authored
When MES is enabled KIQ is not available. Return an error when someone uses the debugfs preempt test interface in that case. Acked-by:
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Leo Li authored
[Why] DCN IPS interoperates with other system idle power features, such as Zstates. On DCN35, there is a known issue where system Z8 + DCN IPS2 causes a hard hang. We observe this on systems where the SBIOS allows Z8. Though there is a SBIOS fix, there's no guarantee that users will get it any time soon, or even install it. A workaround is needed to prevent this from rearing its head in the wild. [How] For DCN35, check the pmfw version to determine whether the SBIOS has the fix. If not, set IPS1+RCG as the deepest possible state in all cases except for s0ix and display off (DPMS). Otherwise, enable all IPS Signed-off-by:
Harry Wentland <harry.wentland@amd.com> Signed-off-by:
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Sunil Khatri authored
log message "Dumping IP State Completed" needs to be logged only once when state dumping is complete. Hence moving it out of the for loop. Signed-off-by:
Sunil Khatri <sunil.khatri@amd.com> Acked-by:
Trigger Huang <Trigger.Huang@amd.com> Signed-off-by:
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Victor Zhao authored
[background] when unloading amdgpu driver right after running a workload, drain_workqueue is causing "Fence fallback timer expired on ring sdma0.0". Under sriov, this issue will cause sriov full access timeout and a reset happening. move drain_workqueue before shutdown is set to allow ih process and before enter full access under sriov to avoid full access time cost. Signed-off-by:
Victor Zhao <Victor.Zhao@amd.com> Reviewed-by:
Feifei Xu <Feifei.Xu@amd.com> Signed-off-by:
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Trigger Huang authored
Do the coredump immediately after a job timeout to get a closer representation of GPU's error status. V2: This will skip printing vram_lost as the GPU reset is not happened yet (Alex) V3: Unconditionally call the core dump as we care about all the reset functions(soft-recovery and queue reset and full adapter reset, Alex) V4: Do the dump after adev->job_hang = true (Sunil) Signed-off-by:
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Trigger Huang authored
The vm lost status can only be obtained after a GPU reset occurs, but sometimes a dev core dump can be happened before GPU reset. So a new argument is added to tell the dev core dump implementation whether to skip printing the vram_lost status in the dump. And this patch is also trying to decouple the core dump function from the GPU reset function, by replacing the argument amdgpu_reset_context with amdgpu_job to specify the context for core dump. V2: Inform user if VRAM lost check is skipped so users don't assume VRAM wasn't lost (Alex) Signed-off-by:
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Alex Deucher authored
Pending extended validation. Reviewed-and-tested-by:
Jiadong Zhu <Jiadong.Zhu@amd.com> Acked-by:
Felix Kuehling <felix.kuehling@amd.com> Signed-off-by:
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Alex Deucher authored
Add this flag to enable experimental resets for testing before they are fully validated. Reviewed-and-tested-by:
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Fangzhi Zuo authored
[why] It is to fix in try_disable_dsc() due to misrevert of commit 338567d1 ("drm/amd/display: Fix MST BW calculation Regression") [How] Fix restoring minimum compression bw by 'max_kbps', instead of native bw 'stream_kbps' Signed-off-by:
Fangzhi Zuo <Jerry.Zuo@amd.com> Reviewed-by:
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- 27 Aug, 2024 18 commits
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Alex Deucher authored
Always reprogram the hardware state on init. This ensures the PMFW state is explicitly programmed and we are not relying on the default PMFW state. Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/3131Reviewed-by:
Kenneth Feng <kenneth.feng@amd.com> Signed-off-by:
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Zaeem Mohamed authored
Remove unnecessary TODO from spl_os_types.h Reviewed-by:
Zaeem Mohamed <zaeem.mohamed@amd.com> Tested-by:
Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by:
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Zaeem Mohamed authored
Use appropriate SPDX copyright for spl_os_types.h Reviewed-by:
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Fangzhi Zuo authored
Add DSC log in each critical routines to facilitate debugging. Reviewed-by:
Rodrigo Siqueira <rodrigo.siqueira@amd.com> Signed-off-by:
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Aric Cyr authored
This version brings along the following fixes: - Fix MS/MP mismatches in dml21 for dcn401 - Resolved Coverity issues - Add back quality EASF and ISHARP and dc dependency changes - Add sharpness support for windowed YUV420 video - Add improvements for text display and HDR DWM and MPO - Fix Synaptics Cascaded Panamera DSC Determination - Allocate DCN35 clock table transfer buffers in GART - Add Replay Low Refresh Rate parameters in dc type Acked-by:
Aric Cyr <aric.cyr@amd.com> Signed-off-by:
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Samson Tam authored
[Why] Previous only applied sharpness for fullscreen YUV420 video. [How] Remove fullscrene restriction and apply sharpness for windowed YUV420 video as well. Reviewed-by:
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Samson Tam authored
[Why] Tune settings for improved text display. Handle differences between DWM and MPO in HDR path. [How] Update sharpener LBA table. Use HDR multiplier to calculate scalar matrix coefficients for HDR RGB MPO path. Update unit tests. Reviewed-by:
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Dennis Chan authored
Why: To supported Low Refresh Rate panel for Replay Feature, Adding some parameters to record Low Refresh Rate information. Reviewed-by:
Robin Chen <robin.chen@amd.com> Signed-off-by:
Dennis Chan <dennis.chan@amd.com> Signed-off-by:
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Samson Tam authored
[Why] Addressed previous issues with quality changes and new issues due to rolling back quality changes. [How] This reverts commit f9e67598, fixes merge conflicts, and fixed some formatting errors. Store current sharpness level for each pregen table to minimize calculating sharpness table every time. Disable dynamic ODM when sharpness is enabled. Reviewed-by:
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Nicholas Kazlauskas authored
[Why] We want to avoid arming the HPD timer in firmware when preparing for S0i3 entry when DC is considered in D3. [How] Notify DMCUB of the power state transitions so it can decide to arm the HPD timer for idle in DCN35 only in D0. Reviewed-by:
Ovidiu Bunea <Ovidiu.Bunea@amd.com> Signed-off-by:
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Fangzhi Zuo authored
Synaptics Cascaded Panamera topology needs to unconditionally acquire root aux for dsc decoding. Reviewed-by:
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ChunTao Tso authored
[Why] Because sometime DMUB GPINT will time out, it will cause we return 0 as residency number. [How] Retry to avoid this happened. Reviewed-by:
ChunTao Tso <ChunTao.Tso@amd.com> Signed-off-by:
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Nicholas Kazlauskas authored
[Why] Request from PMFW to use GART for clock table transfer tables as framebuffer is being deprecated on APU. [How] Switch over to GART via the allocation flag. Reviewed-by:
Sung joon Kim <sungjoon.kim@amd.com> Signed-off-by:
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Aurabindo Pillai authored
translate_by_source need not be set for DCN401 onwards since cursor cursor composition comes after scaler in the hardware pipeline. Hence offset calculation has been reworked, and this setting is not necessary to be enabled anymore. Reviewed-by:
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Daniel Sa authored
[WHY] Remove coverity issues that were originally ignored. [HOW] Ran coverity locally on driver, used output report to find existing coverity issues, resolved them Reviewed-by:
Nicholas Choi <nicholas.choi@amd.com> Signed-off-by:
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Dillon Varone authored
[WHY] Prefetch calculations did not guarantee that bandwidth required in mode support was less than mode programming which can cause failures. [HOW] Fix bandwidth calculations to assume fixed times for OTO schedule, and choose which schedule to use based on time to fetch pixel data. Reviewed-by:
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Alvin Lee authored
[Description] Before every full update we must wait for all pending updates to be cleared - this is particularly important for minimal transitions because if we don't wait for pending cleared, it will be as if there was no minimal transition at all. In OTG we must read 3 different status registers for pending cleared, one specifically for OTG updates, one specifically for OPTC updates, and the last for surface related updates Reviewed-by:
Alvin Lee <Alvin.Lee2@amd.com> Signed-off-by:
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Ahmed, Muhammad authored
[why] post_divider_value should not be 0. Reviewed-by:
Charlene Liu <charlene.liu@amd.com> Signed-off-by:
Ahmed, Muhammad <Ahmed.Ahmed@amd.com> Signed-off-by:
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