- 25 Apr, 2023 2 commits
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Stephen Boyd authored
- Frequency Hopping (FHCTL) on MediaTek MT6795, MT8173, MT8192 and MT8195 SoCs - Converted most Mediatek clock drivers to struct platform_driver - MediaTek clock drivers can be built as modules - Mediatek MT8188 SoC clk drivers - Clock driver for Sunplus SP7021 SoC - Reimplement Loongson-1 clk driver with DT support - Clk driver support for Loongson-2 SoCs - Migrate socfpga clk driver to of_clk_add_hw_provider() * clk-mediatek: (84 commits) clk: mediatek: fhctl: Mark local variables static clk: mediatek: Use right match table, include mod_devicetable clk: mediatek: Add MT8188 adsp clock support clk: mediatek: Add MT8188 imp i2c wrapper clock support clk: mediatek: Add MT8188 wpesys clock support clk: mediatek: Add MT8188 vppsys1 clock support clk: mediatek: Add MT8188 vppsys0 clock support clk: mediatek: Add MT8188 vencsys clock support clk: mediatek: Add MT8188 vdosys1 clock support clk: mediatek: Add MT8188 vdosys0 clock support clk: mediatek: Add MT8188 vdecsys clock support clk: mediatek: Add MT8188 mfgcfg clock support clk: mediatek: Add MT8188 ipesys clock support clk: mediatek: Add MT8188 imgsys clock support clk: mediatek: Add MT8188 ccusys clock support clk: mediatek: Add MT8188 camsys clock support clk: mediatek: Add MT8188 infrastructure clock support clk: mediatek: Add MT8188 peripheral clock support clk: mediatek: Add MT8188 topckgen clock support clk: mediatek: Add MT8188 apmixedsys clock support ... * clk-sunplus: clk: Add Sunplus SP7021 clock driver * clk-loongson: clk: clk-loongson2: add clock controller driver support dt-bindings: clock: add loongson-2 boot clock index MAINTAINERS: remove obsolete file entry in MIPS/LOONGSON1 ARCHITECTURE MIPS: loongson32: Update the clock initialization clk: loongson1: Re-implement the clock driver clk: loongson1: Remove the outdated driver dt-bindings: clock: Add Loongson-1 clock * clk-socfpga: clk: socfpga: arria10: use of_clk_add_hw_provider and improve error handling clk: socfpga: use of_clk_add_hw_provider and improve error handling clk: socfpga: arria10: use of_clk_add_hw_provider and improve error handling clk: socfpga: use of_clk_add_hw_provider and improve error handling clk: socfpga: arria10: use of_clk_add_hw_provider and improve error handling clk: socfpga: use of_clk_add_hw_provider and improve error handling
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Stephen Boyd authored
Merge branches 'clk-cleanup', 'clk-aspeed', 'clk-dt', 'clk-renesas' and 'clk-skyworks' into clk-next - Support for i3c clks on Aspeed ast2600 SoCs - Clock driver for Skyworks Si521xx I2C PCIe clock generators * clk-cleanup: clk: microchip: fix potential UAF in auxdev release callback clk: sifive: make SiFive clk drivers depend on ARCH_ symbols clk: stm32h7: Remove an unused field in struct stm32_fractional_divider clk: tegra20: fix gcc-7 constant overflow warning clock: milbeaut: use devm_platform_get_and_ioremap_resource() clk: Print an info line before disabling unused clocks clk: ti: Use of_address_to_resource() clk: remove unnecessary (void*) conversions clk: at91: clk-sam9x60-pll: fix return value check clk: visconti: remove unused visconti_pll_provider::regmap * clk-aspeed: dt-bindings: clock: ast2600: Expand comment on reset definitions clk: ast2600: Add comment about combined clock + reset handling dt-bindings: clock: ast2600: remove IC36 & I3C7 clock definitions clk: ast2600: Add full configs for I3C clocks dt-bindings: clock: ast2600: Add top-level I3C clock clk: ast2600: allow empty entries in aspeed_g6_gates * clk-dt: clk: mediatek: clk-pllfh: fix missing of_node_put() in fhctl_parse_dt() clk: Use of_property_present() for testing DT property presence * clk-renesas: clk: renesas: r8a77980: Add I2C5 clock clk: rs9: Add support for 9FGV0441 clk: rs9: Support device specific dif bit calculation dt-bindings: clk: rs9: Add 9FGV0441 clk: rs9: Check for vendor/device ID clk: renesas: Convert to platform remove callback returning void clk: renesas: r9a06g032: Improve clock tables clk: renesas: r9a06g032: Document structs clk: renesas: r9a06g032: Drop unused fields clk: renesas: r9a06g032: Improve readability clk: renesas: r8a77980: Add Z2 clock clk: renesas: r8a77970: Add Z2 clock clk: renesas: r8a77995: Fix VIN parent clock clk: renesas: r8a77980: Add VIN clocks clk: renesas: r8a779g0: Add VIN clocks clk: renesas: r8a779g0: Add ISPCS clocks clk: renesas: r8a779g0: Add CSI-2 clocks clk: renesas: r8a779g0: Add thermal clock clk: renesas: r8a779g0: Add Audio clocks clk: renesas: cpg-mssr: Update MSSR register range for R-Car V4H * clk-skyworks: clk: si521xx: Clock driver for Skyworks Si521xx I2C PCIe clock generators dt-bindings: clk: si521xx: Add Skyworks Si521xx I2C PCIe clock generators
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- 13 Apr, 2023 1 commit
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Conor Dooley authored
Similar to commit 1c11289b ("peci: cpu: Fix use-after-free in adev_release()"), the auxiliary device is not torn down in the correct order. If auxiliary_device_add() fails, the release callback will be called twice, resulting in a UAF. Due to timing, the auxdev code in this driver "took inspiration" from the aforementioned commit, and thus its bugs too! Moving auxiliary_device_uninit() to the unregister callback instead avoids the issue. CC: stable@vger.kernel.org Fixes: b56bae2d ("clk: microchip: mpfs: add reset controller") Signed-off-by:
Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20230413-critter-synopsis-dac070a86cb4@spudSigned-off-by:
Stephen Boyd <sboyd@kernel.org>
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- 10 Apr, 2023 3 commits
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Tom Rix authored
smatch reports drivers/clk/mediatek/clk-fhctl.c:17:27: warning: symbol 'fhctl_offset_v1' was not declared. Should it be static? drivers/clk/mediatek/clk-fhctl.c:30:27: warning: symbol 'fhctl_offset_v2' was not declared. Should it be static? These variables are only used in one file so should be static. Signed-off-by:
Tom Rix <trix@redhat.com> Link: https://lore.kernel.org/r/20230406010935.1944976-1-trix@redhat.com Fixes: 8da312d6 ("clk: mediatek: fhctl: Add support for older fhctl register layout") Signed-off-by:
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Conor Dooley authored
As part of converting RISC-V SOC_FOO symbols to ARCH_FOO to match the use of such symbols on other architectures, convert the SiFive clk drivers to use the new symbol. Signed-off-by:
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Stephen Boyd authored
Merge tag 'renesas-clk-for-v6.4-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-renesas Pull one more Renesas clk driver update from Geert Uytterhoeven: - Add I2C5 clock on R-Car V3H * tag 'renesas-clk-for-v6.4-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers: clk: renesas: r8a77980: Add I2C5 clock
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- 04 Apr, 2023 1 commit
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Stephen Boyd authored
This is copy/pasta that breaks modular builds. Fix the match table to use the right pointer, or the right device table type. And while we're including the header, fix the order to be linux, dt-bindings, and finally local. Cc: Garmin.Chang <Garmin.Chang@mediatek.com> Cc: Chen-Yu Tsai <wenst@chromium.org> Reviewed-by:
AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Fixes: f42b9e9a ("clk: mediatek: Add MT8188 wpesys clock support") Fixes: 0d2f2cef ("clk: mediatek: Add MT8188 adsp clock support") Fixes: e4aaa60e ("clk: mediatek: Add MT8188 vdosys0 clock support") Fixes: cfa4609f ("clk: mediatek: Add MT8188 vdosys1 clock support") Fixes: bb87c110 ("clk: mediatek: Add MT8188 vencsys clock support") Reported-by:
kernel test robot <lkp@intel.com> Link: https://lore.kernel.org/oe-kbuild-all/202304011039.UBDX1UOT-lkp@intel.com/ Link: https://lore.kernel.org/oe-kbuild-all/202304020649.QO2HlpD5-lkp@intel.com/ Link: https://lore.kernel.org/oe-kbuild-all/202304021055.WDhQPcoS-lkp@intel.com/Signed-off-by:
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- 03 Apr, 2023 1 commit
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Christophe JAILLET authored
'mmask' has never been used in this driver. Remove it. Signed-off-by:
Christophe JAILLET <christophe.jaillet@wanadoo.fr> Link: https://lore.kernel.org/r/e08a470fbd6151ebd83a548714c08807a80a8ad0.1680364296.git.christophe.jaillet@wanadoo.frSigned-off-by:
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- 31 Mar, 2023 19 commits
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Garmin.Chang authored
Add MT8188 adsp clock controller which provides clock gate control for Audio DSP. Signed-off-by:
Garmin.Chang <Garmin.Chang@mediatek.com> Reviewed-by:
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Garmin.Chang authored
Add MT8188 imp i2c wrapper clock controllers which provide clock gate control in I2C IP blocks. Signed-off-by:
Chen-Yu Tsai <wenst@chromium.org> Reviewed-by:
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Garmin.Chang authored
Add MT8188 wpesys clock controllers which provide clock gate control in Wrapping Engine. Signed-off-by:
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Garmin.Chang authored
Add MT8188 vppsys1 clock controller which provides clock gate controller for Video Processor Pipe. Signed-off-by:
Matthias Brugger <matthias.bgg@gmail.com> Reviewed-by:
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Garmin.Chang authored
Add MT8188 vppsys0 clock controller which provides clock gate controller for Video Processor Pipe. Signed-off-by:
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Garmin.Chang authored
Add MT8188 vencsys clock controllers which provide clock gate control for video encoder. Signed-off-by:
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Garmin.Chang authored
Add MT8188 vdosys1 clock controller which provides clock gate control in video system. This is integrated with mtk-mmsys driver which will populate device by platform_device_register_data to start vdosys clock driver. Signed-off-by:
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Garmin.Chang authored
Add MT8188 vdosys0 clock controller which provides clock gate control in video system. This is integrated with mtk-mmsys driver which will populate device by platform_device_register_data to start vdosys clock driver. Signed-off-by:
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Garmin.Chang authored
Add MT8188 vdec clock controllers which provide clock gate control for video decoder. Signed-off-by:
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Garmin.Chang authored
Add MT8188 mfg clock controller which provides clock gate control for GPU. Signed-off-by:
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Garmin.Chang authored
Add MT8188 ipesys clock controller which provides clock gate control for Image Process Engine. Signed-off-by:
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Garmin.Chang authored
Add MT8188 imgsys clock controllers which provide clock gate control for image IP blocks. Signed-off-by:
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Garmin.Chang authored
Add MT8188 ccusys clock controller which provides clock gate control in Camera Computing Unit. Signed-off-by:
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Garmin.Chang authored
Add MT8188 camsys clock controllers which provide clock gate control for camera IP blocks. Signed-off-by:
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Garmin.Chang authored
Add MT8188 infrastructure clock controller which provides clock gate control for basic IP like pwm, uart, spi and so on. Signed-off-by:
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Garmin.Chang authored
Add MT8188 peripheral clock controller which provides clock gate control for ethernet/flashif/pcie/ssusb. Signed-off-by:
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Garmin.Chang authored
Add MT8188 topckgen clock controller which provides muxes, dividers to handle variety clock selection in other IP blocks. Signed-off-by:
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Garmin.Chang authored
Add MT8188 apmixedsys clock controller which provides Plls generated from SoC 26m and ssusb clock gate control. Signed-off-by:
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Garmin.Chang authored
Add the new binding documentation for system clock and functional clock on MediaTek MT8188. Signed-off-by:
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20230331123621.16167-2-Garmin.Chang@mediatek.comSigned-off-by:
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- 30 Mar, 2023 1 commit
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Nikita Yushchenko authored
The MSSR clock definition for I2C5 was missing. Add it. Signed-off-by:
Nikita Yushchenko <nikita.yoush@cogentembedded.com> Reviewed-by:
Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20230328033902.830269-1-nikita.yoush@cogentembedded.comSigned-off-by:
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- 29 Mar, 2023 3 commits
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Arnd Bergmann authored
Older gcc versions get confused by comparing a u32 value to a negative constant in a switch()/case block: drivers/clk/tegra/clk-tegra20.c: In function 'tegra20_clk_measure_input_freq': drivers/clk/tegra/clk-tegra20.c:581:2: error: case label does not reduce to an integer constant case OSC_CTRL_OSC_FREQ_12MHZ: ^~~~ drivers/clk/tegra/clk-tegra20.c:593:2: error: case label does not reduce to an integer constant case OSC_CTRL_OSC_FREQ_26MHZ: Make the constants unsigned instead. Signed-off-by:
Arnd Bergmann <arnd@arndb.de> Link: https://lore.kernel.org/r/20230227085914.2560984-1-arnd@kernel.orgSigned-off-by:
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Minghao Chi authored
Convert platform_get_resource(), devm_ioremap_resource() to a single call to devm_platform_get_and_ioremap_resource(), as this is exactly what this function does. Signed-off-by:
Minghao Chi <chi.minghao@zte.com.cn> Link: https://lore.kernel.org/r/202211111439357842458@zte.com.cnSigned-off-by:
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Konrad Dybcio authored
Currently, the regulator framework informs us before calling into their unused cleanup paths, which eases at least some debugging. The same could be beneficial for clocks, so that random shutdowns shortly after most initcalls are done can be less of a guess. Add a pr_info before disabling unused clocks to do so. Reviewed-by:
Marijn Suijten <marijn.suijten@somainline.org> Signed-off-by:
Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20230307132928.3887737-1-konrad.dybcio@linaro.orgSigned-off-by:
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- 27 Mar, 2023 9 commits
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Yinbo Zhu authored
This driver provides support for clock controller on Loongson-2 SoC, the Loongson-2 SoC uses a 100MHz clock as the PLL reference clock, there are five independent PLLs inside, each of which PLL can provide up to three sets of frequency dependent clock outputs. Signed-off-by:
Yinbo Zhu <zhuyinbo@loongson.cn> Link: https://lore.kernel.org/r/20230323025229.2971-2-zhuyinbo@loongson.cnSigned-off-by:
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Yinbo Zhu authored
The Loongson-2 boot clock was used to spi and lio peripheral and this patch was to add boot clock index number. Signed-off-by:
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Alexander Stein authored
This model is similar to 9FGV0241, but the DIFx bits start at bit 0. Signed-off-by:
Alexander Stein <alexander.stein@ew.tq-group.com> Reviewed-by:
Marek Vasut <marex@denx.de> Link: https://lore.kernel.org/r/20230310075535.3476580-4-alexander.stein@ew.tq-group.comSigned-off-by:
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Alexander Stein authored
The calculation DIFx is BIT(n) +1 is only true for 9FGV0241. With additional devices this is getting more complicated. Support a base bit for the DIF calculation, currently only devices with consecutive bits are supported, e.g. the 6-channel device needs additional logic. Signed-off-by:
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Alexander Stein authored
This is a 4-channel variant of 9FGV series. Signed-off-by:
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Alexander Stein authored
This is in preparation to support additional devices which have different IDs as well as a slightly different register layout. Signed-off-by:
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Marek Vasut authored
Add driver for the Skyworks Si521xx PCIe clock generators. Supported models are Si52144/Si52146/Si52147, tested model is Si52144. It should be possible to add Si5213x series as well. Signed-off-by:
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Marek Vasut authored
Add binding for Skyworks Si521xx PCIe clock generators. This binding is designed to support Si52144/Si52146/Si52147 series I2C PCIe clock generators, tested model is Si52144. It should be possible to add Si5213x series as well. Reviewed-by:
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Lukas Bulwahn authored
Commit c4649611 ("clk: loongson1: Remove the outdated driver") removes all files matching the pattern drivers/*/*/*loongson1*, but misses to adjust the file entry for MIPS/LOONGSON1 ARCHITECTURE in MAINTAINERS. Hence, ./scripts/get_maintainer.pl --self-test=patterns complains about a broken reference. Remove this file entry in MIPS/LOONGSON1 ARCHITECTURE. Signed-off-by:
Lukas Bulwahn <lukas.bulwahn@gmail.com> Link: https://lore.kernel.org/r/20230323121437.28239-1-lukas.bulwahn@gmail.comAcked-by:
Keguang Zhang <keguang.zhang@gmail.com> Signed-off-by:
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