1. 03 Mar, 2016 1 commit
    • Kedareswara rao Appana's avatar
      dmaengine: xilinx_vdma: Improve SG engine handling · 7096f36e
      Kedareswara rao Appana authored
      The current driver allows user to queue up multiple segments
      on to a single transaction descriptor. User will submit this single desc
      and in the issue_pending() we decode multiple segments and submit to SG HW engine.
      We free up the allocated_desc when it is submitted to the HW.
      
      Existing code prevents the user to prepare multiple trasactions at same time as
      we are overwrite with the allocated_desc.
      
      The best utilization of HW SG engine would happen if we collate the pending
      list when we start dma this patch updates the same.
      Signed-off-by: default avatarKedareswara rao Appana <appanad@xilinx.com>
      Signed-off-by: default avatarVinod Koul <vinod.koul@intel.com>
      7096f36e
  2. 24 Jan, 2016 39 commits