- 13 Dec, 2023 38 commits
-
-
Evan Quan authored
To protect PMFW from being overloaded. Signed-off-by:
Evan Quan <quanliangl@hotmail.com> Reviewed-by:
Mario Limonciello <mario.limonciello@amd.com> Signed-off-by:
Ma Jun <Jun.Ma2@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
-
Evan Quan authored
With WBRF feature supported, as a driver responding to the frequencies, amdgpu driver is able to do shadow pstate switching to mitigate possible interference(between its (G-)DDR memory clocks and local radio module frequency bands used by Wifi 6/6e/7). -- v1->v2: - update the prompt for feature support(Lijo) v8->v9: - update parameter document for smu_wbrf_event_handler(Simon) v9->v10: v10->v11: - correct the logics for wbrf range sorting(Lijo) v13: - Fix the format issue (IIpo Jarvinen) Signed-off-by:
-
Evan Quan authored
Add those data structures to support Wifi RFI mitigation feature. Signed-off-by:
-
Alex Deucher authored
Immutable branch between pdx86 amd wbrf branch and wifi / amdgpu due for the v6.8 merge window platform-drivers-x86-amd-wbrf-v6.8-1: v6.7-rc1 + AMD WBRF support for merging into the wifi subsys and amdgpu driver for 6.8. Signed-off-by: -
Felix Kuehling authored
Use drm_gem_prime_fd_to_handle to import DMABufs for interop. This ensures that a GEM handle is created on import and that obj->dma_buf will be set and remain set as long as the object is imported into KFD. Signed-off-by:
Felix Kuehling <Felix.Kuehling@amd.com> Reviewed-by:
Ramesh Errabolu <Ramesh.Errabolu@amd.com> Reviewed-by:
Xiaogang.Chen <Xiaogang.Chen@amd.com> Acked-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
-
Felix Kuehling authored
Create GEM handles for exporting DMABufs using GEM-Prime APIs. The GEM handles are created in a drm_client_dev context to avoid exposing them in user mode contexts through a DMABuf import. Signed-off-by:
-
Vignesh Chander authored
1. Use the mirrored topology info to fill links for VF. The new solution is required to simplify and optimize host driver logic. Only use the new solution for VFs that support full duplex and extended_peer_link_info otherwise the info would be incomplete. 2. avoid calling extended_link_info on VF as its not supported Signed-off-by:
Vignesh Chander <Vignesh.Chander@amd.com> Reviewed-by:
Zhigang Luo <zhigang.luo@amd.com> Reviewed-by:
Jonathan Kim <jonathan.kim@amd.com> Signed-off-by:
-
Harshit Mogalapalli authored
'wb_info' needs to be freed on error paths or it would leak the memory. Smatch pointed this out. Fixes: c81e13b9 ("drm/amd/display: Hande writeback request from userspace") Signed-off-by:
Harshit Mogalapalli <harshit.m.mogalapalli@oracle.com> Reviewed-by:
Alex Hung <alex.hung@amd.com> Signed-off-by:
-
Joshua Ashton authored
Multiplier to 'gain' the plane. When PQ is decoded using the fixed func transfer function to the internal FP16 fb, 1.0 -> 80 nits (on AMD at least) When sRGB is decoded, 1.0 -> 1.0. Therefore, 1.0 multiplier = 80 nits for SDR content. So if you want, 203 nits for SDR content, pass in (203.0 / 80.0). v4: - comment about the PQ TF need for L-to-NL (from Harry's review) Reviewed-by:
Harry Wentland <harry.wentland@amd.com> Signed-off-by:
Joshua Ashton <joshua@froggi.es> Co-developed-by:
Melissa Wen <mwen@igalia.com> Signed-off-by:
-
Melissa Wen authored
Brief documentation about pre-defined transfer function usage on AMD display driver and standardized EOTFs and inverse EOTFs. v3: - Document BT709 OETF (Pekka) - Fix description of sRGB and pure power funcs (Pekka) v4: - Add description of linear and non-linear forms (Harry) Reviewed-by:
-
Melissa Wen authored
Instead of relying on color block names to get the transfer function intention regarding encoding pixel's luminance, define supported Electro-Optical Transfer Functions (EOTFs) and inverse EOTFs, that includes pure gamma or standardized transfer functions. v3: - squash linear and unity TFs to identity (Pekka) - define the right TFs for BT.709 (Pekka and Harry) - add comment about AMD TF coefficients Suggested-by:
-
Joshua Ashton authored
Allow userspace to tell the kernel driver the input space and, therefore, uses correct predefined transfer function (TF) to go from encoded values to linear values. v2: - rename TF enum prefix from DRM_ to AMDGPU_ (Harry) - remove HLG TF Reviewed-by:
-
Mario Limonciello authored
When screen brightness is rapidly changed and PSR-SU is enabled the display hangs on panels with this TCON even on the latest DCN 3.1.4 microcode (0x8002a81 at this time). This was disabled previously as commit 072030b1 ("drm/amd: Disable PSR-SU on Parade 0803 TCON") but reverted as commit 1e66a17c ("Revert "drm/amd: Disable PSR-SU on Parade 0803 TCON"") in favor of testing for a new enough microcode (commit cd2e31a9 ("drm/amd/display: Set minimum requirement for using PSR-SU on Phoenix")). As hangs are still happening specifically with this TCON, disable PSR-SU again for it until it can be root caused. Cc: stable@vger.kernel.org Cc: aaron.ma@canonical.com Cc: binli@gnome.org Cc: Marc Rossi <Marc.Rossi@amd.com> Cc: Hamza Mahfooz <Hamza.Mahfooz@amd.com> Signed-off-by:
-
Aric Cyr authored
Summary: Bug fixes for: * DCN35 power gating * P-state change, & prefetch logic * ABM * DP 2.1 Acked-by:
Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by:
Aric Cyr <aric.cyr@amd.com> Signed-off-by:
-
Charlene Liu authored
[why] Power up and power down has reverted programming order. also make sure disable root clock last. Reviewed-by:
Muhammad Ahmed <ahmed.ahmed@amd.com> Acked-by:
Charlene Liu <charlene.liu@amd.com> Signed-off-by:
-
Alvin Lee authored
[Description] - When we're in a no plane config, DCN is always asserting P-State allow - This creates a scenario where the P-State blackout can start just as VUPDATE takes place and transitions the DCN config to a one where one or more HUBP's are active which can result in underflow - To fix this issue, force p-state disallow and unforce after the transition from no planes case -> one or more planes active Reviewed-by:
Samson Tam <samson.tam@amd.com> Acked-by:
Alvin Lee <alvin.lee2@amd.com> Signed-off-by:
-
Alvin Lee authored
[Description] For mode programming we want to extend the prefetch as much as possible (up to oto, or as long as we can for equ) if we're not already applying the 60us prefetch requirement. This is to avoid intermittent underflow issues during prefetch. The prefetch extension is applied under the following scenarios: 1. We're in prefetch mode 1 (i.e. we don't support MCLK switch in blank) 2. We're using subvp or drr methods of p-state switch, in which case we we don't care if prefetch takes up more of the blanking time Mode programming typically chooses the smallest prefetch time possible (i.e. highest bandwidth during prefetch) presumably to create margin between p-states / c-states that happen in vblank and prefetch. Therefore we only apply this prefetch extension when p-state in vblank is not required (UCLK p-states take up the most vblank time). Reviewed-by:
Jun Lei <jun.lei@amd.com> Acked-by:
-
Sung Joon Kim authored
[why & how] User interface cannot guarantee system is in idle state, so need to ensure we exit idle state before accessing any HW data. Reviewed-by:
Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Acked-by:
Sung Joon Kim <sungkim@amd.com> Signed-off-by:
-
Allen authored
[Why] To match the hardware sequence Reviewed-by:
Allen <allen.pan@amd.com> Signed-off-by:
-
Fangzhi Zuo authored
dtbclk is unavaliable from pmfw. Try to grab the value from bounding box Reviewed-by:
Fangzhi Zuo <jerry.zuo@amd.com> Signed-off-by:
-
Michael Strauss authored
[WHY] Introduces regression with DP2 native displays [HOW] Revert the change Reviewed-by:
Michael Strauss <michael.strauss@amd.com> Signed-off-by:
-
Aurabindo Pillai authored
FP guard is valid for all recent asics, not just RV, so fix the comment. Reviewed-by:
Chaitanya Dhere <chaitanya.dhere@amd.com> Acked-by:
-
Taimur Hassan authored
[Why & How] HostVMMinPageSize is expected to be in KB according to spec, the checks later down the line reflect this as well. Reviewed-by:
Taimur Hassan <syed.hassan@amd.com> Signed-off-by:
-
Ran Shi authored
why: With DP2.1a expansion we are allowing DP40 cables to do UHBR13.5 how: Assume UHBR10 means UHBR13.5 also for unknown cable type and passive cable type. Reviewed-by:
George Shen <george.shen@amd.com> Acked-by:
Ran Shi <ran.shi@amd.com> Signed-off-by:
-
Aurabindo Pillai authored
Reviewed-by:
-
Joshua Aberback authored
Reviewed-by:
Dillon Varone <dillon.varone@amd.com> Acked-by:
Joshua Aberback <joshua.aberback@amd.com> Signed-off-by:
-
Ma Jun authored
Remove redundant functions members of pptable_funcs and change the function type as static because they are not called by other files. Signed-off-by:
Yang Wang <kevinyang.wang@amd.com> Signed-off-by:
-
Saleemkhan Jamadar authored
Doorbell is configured during start of each playback. v1 - add comment for the doorbell programming change Signed-off-by:
Saleemkhan Jamadar <saleemkhan.jamadar@amd.com> Acked-by:
Leo Liu <leo.liu@amd.com> Reviewed-by:
Veerabadhran Gopalakrishnan <Veerabadhran.Gopalakrishnan@amd.com> Signed-off-by:
-
Lijo Lazar authored
Replace direct usage of adev->ip_versions with amdgpu_ip_version. Signed-off-by:
Lijo Lazar <lijo.lazar@amd.com> Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by:
-
Melissa Wen authored
Hook up driver-specific atomic operations for managing AMD color properties. Create AMD driver-specific color management properties and attach them according to HW capabilities defined by `struct dc_color_caps`. First add plane degamma LUT properties that means user-blob and its size. We will add more plane color properties in the next patches. In addition, we define AMD_PRIVATE_COLOR to guard these driver-specific plane properties. Plane degamma can be used to linearize input space for arithmetical operations that are more accurate when applied in linear color. v2: - update degamma LUT prop description - move private color operations from amdgpu_display to amdgpu_dm_color v5: - get degamma blob correctly (Joshua) Reviewed-by:
-
Melissa Wen authored
We will add color mgmt properties to DRM planes in the next patches and we want to track when one of this properties change to define atomic commit behaviors. Using a similar approach from CRTC color props, we set a color_mgmt_changed boolean whenever a plane color prop changes. Reviewed-by:
Maxime Ripard <mripard@kernel.org> Signed-off-by:
-
Melissa Wen authored
Place it in drm_property where drm_property_replace_blob and drm_property_lookup_blob live. Then we can use the DRM helper for driver-specific KMS properties too. Reviewed-by:
Liviu Dudau <liviu.dudau@arm.com> Signed-off-by:
-
Melissa Wen authored
DRM_OBJECT_MAX_PROPERTY limits the number of properties to be attached and we are increasing that value all time we add a new property (generic or driver-specific). In this series, we are adding 13 new KMS driver-specific properties for AMD color manage: - CRTC Gamma enumerated Transfer Function - Plane: Degamma LUT+size+TF, HDR multiplier, shaper LUT+size+TF, 3D LUT+size, blend LUT+size+TF (12) Therefore, just increase DRM_OBJECT_MAX_PROPERTY to a number (64) that accomodates these new properties and gives some room for others, avoiding change this number everytime we add a new KMS property. Reviewed-by:
Simon Ser <contact@emersion.fr> Signed-off-by:
Abhinav Kumar <quic_abhinavk@quicinc.com> Acked-by:
-
Colin Ian King authored
There is a spelling mistake in a smu_print message. Fix it. Signed-off-by:
Colin Ian King <colin.i.king@gmail.com> Signed-off-by:
-
Alex Deucher authored
Part of commit c0358198 ("drm/amdgpu: fix buffer funcs setting order on suspend") got dropped accidently. Add it back. Fixes: c0358198 ("drm/amdgpu: fix buffer funcs setting order on suspend") Signed-off-by:
-
https://gitlab.freedesktop.org/agd5f/linuxDave Airlie authored
amd-drm-next-6.8-2023-12-08: amdgpu: - SR-IOV fixes - DCN 3.5 updates - Backlight fixes - MST fixes - DMCUB fixes - DPIA fixes - Display powergating updates - Enable writeback connectors - Misc code cleanups - Add more register state debugging for aquavanjaram - Suspend fix - Clockgating fixes - SMU 14 updates - PSR fixes - MES logging updates - Misc fixes amdkfd: - SVM fix radeon: - Fix potential memory leaks in error paths Signed-off-by:
Dave Airlie <airlied@redhat.com> From: Alex Deucher <alexander.deucher@amd.com> Link: https://patchwork.freedesktop.org/patch/msgid/20231208205613.4861-1-alexander.deucher@amd.com
-
Dave Airlie authored
Merge tag 'drm-intel-gt-next-2023-12-08' of git://anongit.freedesktop.org/drm/drm-intel into drm-next UAPI Changes: - drm/i915: Implement fdinfo memory stats printing Use the newly added drm_print_memory_stats helper to show memory utilisation of our objects in drm/driver specific fdinfo output. To collect the stats we walk the per memory regions object lists and accumulate object size into the respective drm_memory_stats categories. Cross-subsystem Changes: - Backmerge of drm-next (to bring drm-intel-next for PXP changes) Driver Changes: - Wa_18028616096 now applies to all DG2 (Matt R) - Drop Wa_22014600077 on all DG2 (Matt R) - Add new ATS-M device ID (Haridhar) - More Meteorlake (MTL) workarounds (Matt R, Dnyaneshwar, Jonathan, Gustavo, Radhakrishna) - PMU WARN_ON cleanup on driver unbind (Umesh) - Limit GGTT WC flushing workaround to pre BXT/ICL platforms - Complement implementation for Wa_16018031267 / Wa_16018063123 (Andrzej, Jonathan, Nirmoy, Chris) - Properly print internal GSC engine in trace logs (Tvrtko) - Track gt pm wakerefs (Andrzej) - Fix null deref bugs on perf code when perf is disabled (Harshit, Tvrtko) - Fix __i915_request_create memory leak on driver unbind (Andrzej) - Remove spurious unsupported HuC message on MTL (Daniele) - Read a shadowed mmio register for ggtt flush (Vinay) - Add missing new-line to GT_TRACE (Andrzej) - Add drm_dbgs for critical PXP events (Alan) - Skip pxp init if gt is wedged (Zhanjun) - Replace custom intel runtime_pm tracker with ref_tracker library (Andrzej) - Compiler warning/static checker/coding style cleanups (Arnd, Nirmoy, Soumya, Gilbert, Dorcas, Kunwu, Sam, Tvrtko) - Code structure and helper cleanups (Jani, Tvrtko, Andi) - Selftest improvements (John, Tvrtko, Andrzej) Signed-off-by:
-
Dave Airlie authored
Merge tag 'exynos-drm-next-for-v6.8' of git://git.kernel.org/pub/scm/linux/kernel/git/daeinki/drm-exynos into drm-next One bug fix - Add a missing call to drm_atomic_helper_shutdown() in Exynos DRM driver. This function is necessary during system shutdown and when the driver is unbound. Without this function, components like panels may not shut down properly, potentially leading to power issue as mentioned in the kernel documentation, specially in the "driver instance overview" secstion of 'drm_drv.c'. Two cleanups - Convert '.remove()' callback function in the Exynos DRM platform driver to a version that returns void instead of an integer. - Change connector type of exynos_drm_dpi.c module to DPI. Signed-off-by:
-
- 12 Dec, 2023 2 commits
-
-
Paul Cercueil authored
When exynos_drm_dpi.c was written, DRM_MODE_CONNECTOR_DPI did not exist yet and I guess that's the reason why DRM_MODE_CONNECTOR_VGA was used as the connector type. However, now it makes more sense to use DRM_MODE_CONNECTOR_DPI as the connector type. Signed-off-by:
Paul Cercueil <paul@crapouillou.net> Signed-off-by:
Inki Dae <inki.dae@samsung.com>
-
Uwe Kleine-König authored
The .remove() callback for a platform driver returns an int which makes many driver authors wrongly assume it's possible to do error handling by returning an error code. However the value returned is ignored (apart from emitting a warning) and this typically results in resource leaks. To improve here there is a quest to make the remove callback return void. In the first step of this quest all drivers are converted to .remove_new(), which already returns void. Eventually after all drivers are converted, .remove_new() will be renamed to .remove(). Trivially convert this driver from always returning zero in the remove callback to the void returning variant. Signed-off-by:
Uwe Kleine-König <u.kleine-koenig@pengutronix.de> fix merge conflict and drop duplicated patch description. Signed-off-by:
-
