- 17 May, 2010 40 commits
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Alexander Graf authored
Some times we don't want all capabilities to be available to all our vcpus. One example for that is the OSI interface, implemented in the next patch. In order to have a generic mechanism in how to enable capabilities individually, this patch introduces a new ioctl that can be used for this purpose. That way features we don't want in all guests or userspace configurations can just not be enabled and we're good. Signed-off-by:
Alexander Graf <agraf@suse.de> Signed-off-by:
Avi Kivity <avi@redhat.com>
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Alexander Graf authored
Mac OS X has some applications - namely the Finder - that require alignment interrupts to work properly. So we need to implement them. But the spec for 970 and 750 also looks different. While 750 requires the DSISR and DAR fields to reflect some instruction bits (DSISR) and the fault address (DAR), the 970 declares this as an optional feature. So we need to reconstruct DSISR and DAR manually. Signed-off-by:
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Alexander Graf authored
We get MMIOs with the weirdest instructions. But every time we do, we need to improve our emulator to implement them. So let's do that - this time it's lbzux and lhax's round. Signed-off-by:
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Alexander Graf authored
We have a 32 bit value in the PACA to store XER in. We also do an stw when storing XER in there. But then we load it with ld, completely screwing it up on every entry. Welcome to the Big Endian world. Signed-off-by:
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Alexander Graf authored
BATs can't only be written to, you can also read them out! So let's implement emulation for reading BAT values again. While at it, I also made BAT setting flush the segment cache, so we're absolutely sure there's no MMU state left when writing BATs. Signed-off-by:
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Alexander Graf authored
We emulate the mfsrin instruction already, that passes the SR number in a register value. But we lacked support for mfsr that encoded the SR number in the opcode. So let's implement it. Signed-off-by:
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Alexander Graf authored
When trying to read or store vcpu register data, we should also make sure the vcpu is actually loaded, so we're 100% sure we get the correct values. Signed-off-by:
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Alexander Graf authored
When the guest activates the FPU, we load it up. That's fine when it wasn't activated before on the host, but if it was we end up reloading FPU values from last time the FPU was deactivated on the host without writing the proper values back to the vcpu struct. This patch checks if the FPU is enabled already and if so just doesn't bother activating it, making FPU operations survive guest context switches. Signed-off-by:
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Alexander Graf authored
The current check_ext function reads the instruction and then does the checking. Let's split the reading out so we can reuse it for different functions. Signed-off-by:
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Alexander Graf authored
This patch makes the VSID of mapped pages always reflecting all special cases we have, like split mode. It also changes the tlbie mask to 0x0ffff000 according to the spec. The mask we used before was incorrect. Signed-off-by:
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Alexander Graf authored
DSISR is only defined as 32 bits wide. So let's reflect that in the structs too. Signed-off-by:
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Alexander Graf authored
Userspace can tell us that it wants to trigger an interrupt. But so far it can't tell us that it wants to stop triggering one. So let's interpret the parameter to the ioctl that we have anyways to tell us if we want to raise or lower the interrupt line. Signed-off-by:
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Alexander Graf authored
On PowerPC we can go into MMU Split Mode. That means that either data relocation is on but instruction relocation is off or vice versa. That mode didn't work properly, as we weren't always flushing entries when going into a new split mode, potentially mapping different code or data that we're supposed to. Signed-off-by:
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Avi Kivity authored
Signed-off-by: -
Avi Kivity authored
Acked-by:
Pekka Enberg <penberg@cs.helsinki.fi> Signed-off-by:
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Avi Kivity authored
Direct maps are linear translations for a section of memory, used for real mode or with large pages. As such, they are independent of the guest levels. Teach the mmu about this by making page->role.glevels = 0 for direct maps. This allows direct maps to be shared among real mode and the various paging modes. Signed-off-by: -
Xiao Guangrong authored
- Check reserved bits only if CR4.PAE=1 or CR4.PSE=1 when guest #PF occurs - Fix a typo in reset_rsvds_bits_mask() Signed-off-by:
Xiao Guangrong <xiaoguangrong@cn.fujitsu.com> Reviewed-by:
Marcelo Tosatti <mtosatti@redhat.com> Signed-off-by:
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Marcelo Tosatti authored
Document that KVM_REQ_PENDING_TIMER is implicitly used during guest entry. Signed-off-by:
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Gleb Natapov authored
When CMPXCHG8B is executed without LOCK prefix it is racy. Preserve this behaviour in emulator too. Signed-off-by:
Gleb Natapov <gleb@redhat.com> Signed-off-by:
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Gleb Natapov authored
Decode CMPXCHG8B destination operand in decoding stage. Fixes regression introduced by "If LOCK prefix is used dest arg should be memory" commit. This commit relies on dst operand be decoded at the beginning of an instruction emulation. Signed-off-by:
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Gleb Natapov authored
Make sure that rflags is committed only after successful instruction emulation. Signed-off-by:
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Jan Kiszka authored
Signed-off-by:
Jan Kiszka <jan.kiszka@siemens.com> Signed-off-by:
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Gleb Natapov authored
Unify all conditions that get us back into emulator after returning from userspace. Signed-off-by:
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Gleb Natapov authored
To optimize "rep ins" instruction do IO in big chunks ahead of time instead of doing it only when required during instruction emulation. Signed-off-by:
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Gleb Natapov authored
Currently when string instruction is only partially complete we go back to a guest mode, guest tries to reexecute instruction and exits again and at this point emulation continues. Avoid all of this by restarting instruction without going back to a guest mode, but return to a guest mode each 1024 iterations to allow interrupt injection. Pending exception causes immediate guest entry too. Signed-off-by:
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Gleb Natapov authored
c->eip is never written back in case of emulation failure, so no need to set it to old value. Signed-off-by:
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Gleb Natapov authored
Currently emulation is done outside of emulator so things like doing ins/outs to/from mmio are broken it also makes it hard (if not impossible) to implement single stepping in the future. The implementation in this patch is not efficient since it exits to userspace for each IO while previous implementation did 'ins' in batches. Further patch that implements pio in string read ahead address this problem. Signed-off-by:
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Gleb Natapov authored
in/out emulation is broken now. The breakage is different depending on where IO device resides. If it is in userspace emulator reports emulation failure since it incorrectly interprets kvm_emulate_pio() return value. If IO device is in the kernel emulation of 'in' will do nothing since kvm_emulate_pio() stores result directly into vcpu registers, so emulator will overwrite result of emulation during commit of shadowed register. Signed-off-by:
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Gleb Natapov authored
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Gleb Natapov authored
Add decoding of X,Y parameters from Intel SDM which are used by string instruction to specify source and destination. Use this new decoding to implement movs, cmps, stos, lods in a generic way. Signed-off-by:
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Gleb Natapov authored
All struct operand fields are initialized during decoding for all operand types except OP_MEM, but there is no reason for that. Move OP_MEM operand initialization into decoding stage for consistency. Signed-off-by:
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Gleb Natapov authored
Remove old task switch code from x86.c Signed-off-by:
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Gleb Natapov authored
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Gleb Natapov authored
Implement emulation of 16/32 bit task switch in emulator.c Signed-off-by:
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Gleb Natapov authored
Provide get_cached_descriptor(), set_cached_descriptor(), get_segment_selector(), set_segment_selector(), get_gdt(), write_std() callbacks. Signed-off-by:
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Gleb Natapov authored
When x86_emulate_insn() does not know how to emulate instruction it exits via cannot_emulate label in all cases except when emulating grp3. Fix that. Signed-off-by:
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Gleb Natapov authored
If LOCK prefix is used dest arg should be memory, otherwise instruction should generate #UD. Signed-off-by:
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Gleb Natapov authored
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Gleb Natapov authored
Return X86EMUL_PROPAGATE_FAULT is fault was injected. Also inject #UD for those instruction when appropriate. Signed-off-by:
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Gleb Natapov authored
If CR4.DE=1 access to registers DR4/DR5 cause #UD. Signed-off-by:
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