- 10 Jun, 2023 8 commits
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Dmitry Baryshkov authored
The commit 010c8bba ("drm: msm: adreno: Disable preemption on Adreno 510") added special handling for a510 (this SKU doesn't seem to support preemption, so the driver should clamp nr_rings to 1). However the gpu->revn is not yet set (it is set later, in adreno_gpu_init()) and thus the condition is always false. Check config->rev instead. Fixes: 010c8bba ("drm: msm: adreno: Disable preemption on Adreno 510") Reported-by:
Adam Skladowski <a39.skl@gmail.com> Signed-off-by:
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Tested-by:
Rob Clark <robdclark@chromium.org>
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Rob Clark authored
Allow access to CP_PERFCTR_CP_SEL[n] and RB_PERFCTR_RB_SEL which are used by fdperf and pps-provider (perfetto). Signed-off-by: -
Bjorn Andersson authored
Introduce support for the Adreno A690, found in Qualcomm SC8280XP. Tested-by:
Steev Klimaszewski <steev@kali.org> Reviewed-by:
Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by:
Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by:
Bjorn Andersson <quic_bjorande@quicinc.com> Patchwork: https://patchwork.freedesktop.org/patch/540335/Signed-off-by:
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Rob Clark authored
This is something that can block for arbitrary amounts of time as userspace consumes from the FIFO. So we don't really want this to be in the fence signaling path. Signed-off-by:
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Dmitry Baryshkov authored
If the Adreno SMMU is dma-coherent, allocation will fail unless we disable IO_PGTABLE_QUIRK_ARM_OUTER_WBWA. Skip setting this quirk for the coherent SMMUs (like we have on sm8350 platform). Fixes: 54af0ceb ("arm64: dts: qcom: sm8350: add GPU, GMU, GPU CC and SMMU nodes") Reported-by:
David Heidelberg <david@ixit.cz> Signed-off-by:
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Dmitry Baryshkov authored
The variable ring is not used by msm_parse_deps() and msm_ioctl_gem_submit() and thus can be dropped. Signed-off-by:
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Dmitry Baryshkov authored
Sparse reports plenty of warnings against the a6xx code because of a6xx_gmu::mmio and a6xx_gmu::rscc members. For some reason they were defined as __iomem pointers rather than pointers to __iomem memory. Correct the __iomem attribute. Fixes: 02ef80c5 ("drm/msm/a6xx: update pdc/rscc GMU registers for A640/A650") Reported-by:
kernel test robot <lkp@intel.com> Link: https://lore.kernel.org/oe-kbuild-all/202304070550.NrbhJCvP-lkp@intel.com/Reviewed-by:
Javier Martinez Canillas <javierm@redhat.com> Reviewed-by:
Stephen Boyd <swboyd@chromium.org> Signed-off-by:
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Dmitry Baryshkov authored
Merge branches 'msm-next-lumag-core', 'msm-next-lumag-dpu', 'msm-next-lumag-dp', 'msm-next-lumag-dsi' and 'msm-next-lumag-mdp5' into msm-next-lumag Core: - Add Marijn Suijten as drm/msm reviewer - Adreno A660 bindings - SM8350 MDSS bindings fix DP: - Removed obsolete USB-PD remains - Documented DP compatible string for sm8550 platform DPU: - Added support for DPU on sm6350 and sm6375 platforms - Implemented tearcheck support to support vsync on SM150 and newer platforms - Enabled missing features (DSPP, DSC, split display) on sc8180x, sc8280xp, sm8450 - Enabled writeback on sc7280 - Enabled DSC on msm8998 - Native HDMI output support - Dropped unused features: regdma, GC, IGC - Fixed the DSC flush operations - Simplified QoS handling, removing obsolete and unused features and merging SSPP and WB code paths - Reworked dpu_encoder initialisation path DSI: - Added support for DSI and 28nm DSI PHY on MSM8226 platform - Added support for DSI on sm6350 and sm6375 platforms - Dropped powerup quirks in favour of using pre_enable_prev_first for downstream bridges - Fixed 14nm DSI PHY programming MDP5: - Added support for display controller on MSM8226 platform Signed-off-by:
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- 09 Jun, 2023 2 commits
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Dmitry Baryshkov authored
Move GMU mutex initialization earlier to make sure that it is always initialized. a6xx_destroy can be called from ther failure path before GMU initialization. This fixes the following backtrace: ------------[ cut here ]------------ DEBUG_LOCKS_WARN_ON(lock->magic != lock) WARNING: CPU: 0 PID: 58 at kernel/locking/mutex.c:582 __mutex_lock+0x1ec/0x3d0 Modules linked in: CPU: 0 PID: 58 Comm: kworker/u16:1 Not tainted 6.3.0-rc5-00155-g187c06436519 #565 Hardware name: Qualcomm Technologies, Inc. SM8350 HDK (DT) Workqueue: events_unbound deferred_probe_work_func pstate: 60400005 (nZCv daif +PAN -UAO -TCO -DIT -SSBS BTYPE=--) pc : __mutex_lock+0x1ec/0x3d0 lr : __mutex_lock+0x1ec/0x3d0 sp : ffff800008993620 x29: ffff800008993620 x28: 0000000000000002 x27: ffff47b253c52800 x26: 0000000001000606 x25: ffff47b240bb2810 x24: fffffffffffffff4 x23: 0000000000000000 x22: ffffc38bba15ac14 x21: 0000000000000002 x20: ffff800008993690 x19: ffff47b2430cc668 x18: fffffffffffe98f0 x17: 6f74616c75676572 x16: 20796d6d75642067 x15: 0000000000000038 x14: 0000000000000000 x13: ffffc38bbba050b8 x12: 0000000000000666 x11: 0000000000000222 x10: ffffc38bbba603e8 x9 : ffffc38bbba050b8 x8 : 00000000ffffefff x7 : ffffc38bbba5d0b8 x6 : 0000000000000222 x5 : 000000000000bff4 x4 : 40000000fffff222 x3 : 0000000000000000 x2 : 0000000000000000 x1 : 0000000000000000 x0 : ffff47b240cb1880 Call trace: __mutex_lock+0x1ec/0x3d0 mutex_lock_nested+0x2c/0x38 a6xx_destroy+0xa0/0x138 a6xx_gpu_init+0x41c/0x618 adreno_bind+0x188/0x290 component_bind_all+0x118/0x248 msm_drm_bind+0x1c0/0x670 try_to_bring_up_aggregate_device+0x164/0x1d0 __component_add+0xa8/0x16c component_add+0x14/0x20 dsi_dev_attach+0x20/0x2c dsi_host_attach+0x9c/0x144 devm_mipi_dsi_attach+0x34/0xac lt9611uxc_attach_dsi.isra.0+0x84/0xfc lt9611uxc_probe+0x5b8/0x67c i2c_device_probe+0x1ac/0x358 really_probe+0x148/0x2ac __driver_probe_device+0x78/0xe0 driver_probe_device+0x3c/0x160 __device_attach_driver+0xb8/0x138 bus_for_each_drv+0x84/0xe0 __device_attach+0x9c/0x188 device_initial_probe+0x14/0x20 bus_probe_device+0xac/0xb0 deferred_probe_work_func+0x8c/0xc8 process_one_work+0x2bc/0x594 worker_thread+0x228/0x438 kthread+0x108/0x10c ret_from_fork+0x10/0x20 irq event stamp: 299345 hardirqs last enabled at (299345): [<ffffc38bb9ba61e4>] put_cpu_partial+0x1c8/0x22c hardirqs last disabled at (299344): [<ffffc38bb9ba61dc>] put_cpu_partial+0x1c0/0x22c softirqs last enabled at (296752): [<ffffc38bb9890434>] _stext+0x434/0x4e8 softirqs last disabled at (296741): [<ffffc38bb989669c>] ____do_softirq+0x10/0x1c ---[ end trace 0000000000000000 ]--- Fixes: 4cd15a3e ("drm/msm/a6xx: Make GPU destroy a bit safer") Cc: Douglas Anderson <dianders@chromium.org> Signed-off-by:
Douglas Anderson <dianders@chromium.org> Patchwork: https://patchwork.freedesktop.org/patch/531540/Signed-off-by:
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Kuogee Hsieh authored
The internal_hpd flag is set to true by dp_bridge_hpd_enable() and set to false by dp_bridge_hpd_disable() to handle GPIO pinmuxed into DP controller case. HDP related interrupts can not be enabled until internal_hpd is set to true. At current implementation dp_display_config_hpd() will initialize DP host controller first followed by enabling HDP related interrupts if internal_hpd was true at that time. Enable HDP related interrupts depends on internal_hpd status may leave system with DP driver host is in running state but without HDP related interrupts being enabled. This will prevent external display from being detected. Eliminated this dependency by moving HDP related interrupts enable/disable be done at dp_bridge_hpd_enable/disable() directly regardless of internal_hpd status. Changes in V3: -- dp_catalog_ctrl_hpd_enable() and dp_catalog_ctrl_hpd_disable() -- rewording ocmmit text Changes in V4: -- replace dp_display_config_hpd() with dp_display_host_start() -- move enable_irq() at dp_display_host_start(); Changes in V5: -- replace dp_display_host_start() with dp_display_host_init() Changes in V6: -- squash remove enable_irq() and disable_irq() Fixes: cd198cad ("drm/msm/dp: Rely on hpd_enable/disable callbacks") Signed-off-by:
Kuogee Hsieh <quic_khsieh@quicinc.com> Tested-by: Leonard Lausen <leonard@lausen.nl> # on sc7180 lazor Reviewed-by:
Bjorn Andersson <andersson@kernel.org> Tested-by:
Abhinav Kumar <quic_abhinavk@quicinc.com> Link: https://lore.kernel.org/r/1684878756-17830-1-git-send-email-quic_khsieh@quicinc.comSigned-off-by:
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- 07 Jun, 2023 13 commits
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Dan Carpenter authored
The "vsync_hz" variable is unsigned int so it can't be less than zero. The dpu_kms_get_clk_rate() function used to return a u64 but I previously changed it to return an unsigned long and zero on error so it matches clk_get_rate(). Change the "vsync_hz" type to unsigned long as well and change the error checking to check for zero instead of negatives. This change does not affect runtime at all. It's just a clean up. Signed-off-by:
Dan Carpenter <dan.carpenter@linaro.org> Reviewed-by:
Marijn Suijten <marijn.suijten@somainline.org> Patchwork: https://patchwork.freedesktop.org/patch/541225/ Link: https://lore.kernel.org/r/ZH7vP2Swu8CYpgUL@moroto [DB: fixed debug message] Signed-off-by:
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Abhinav Kumar authored
MSM8998 doesn't have DSC blocks declared in the catalog. Complete DSC 1.1 support for all platforms by adding the missing blocks to MSM8998. Changes in v9: -- add MSM8998 and SC8180x to commit title Changes in v10: -- fix grammar at commit text Changes in v12: -- fix "titil" with "title" at changes in v9 Changes in v14: -- "dsc" tp "DSC" at commit title Changes in v15: -- fix merge conflicts at dpu_5_1_sc8180x.h Changes in v16 -- fix cherry-pick error by deleting both redundant .dsc and .dsc_count assignment from dpu_5_1_sc8180x.h Changes in v17 -- remove sc8180x from both commit title and text -- remove Reviewed-by Signed-off-by:
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Konrad Dybcio authored
Add support for MDSS on SM6375. Reviewed-by:
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Konrad Dybcio authored
Add support for MDSS on SM6350. Reviewed-by:
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Konrad Dybcio authored
Add basic SM6375 support to the DPU1 driver to enable display output. Reviewed-by:
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Konrad Dybcio authored
Add SM6350 support to the DPU1 driver to enable display output. It's worth noting that one entry dpu_qos_lut_entry was trimmed off: {.fl = 0, .lut = 0x0011223344556677 }, due to the lack of support for selecting between portrait and landscape LUT settings (for danger and safe LUTs) and no full support for qseed/non-qseed usescases (for QoS LUT). Signed-off-by:Konrad Dybcio <konrad.dybcio@somainline.org> Reviewed-by:
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Konrad Dybcio authored
Document the SM6375 MDSS. Signed-off-by:
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/541289/ Link: https://lore.kernel.org/r/20230411-topic-straitlagoon_mdss-v6-5-dee6a882571b@linaro.orgSigned-off-by:
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Konrad Dybcio authored
Document the SM6350 MDSS. Signed-off-by:
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Konrad Dybcio authored
SC7180, SM6350 and SM6375 use a rather similar hw setup for DPU, with the main exception being that the last one requires an additional throttle clock. It is not well understood yet, but failing to toggle it on makes the display hardware stall and not output any frames. Document SM6350 and SM6375 DPU. Reviewed-by:
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Konrad Dybcio authored
Add the DSI host found on SM6375. Acked-by:
Rob Herring <robh@kernel.org> Signed-off-by:
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Konrad Dybcio authored
Add the DSI host found on SM6350. Acked-by:
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Dmitry Baryshkov authored
Currently the driver passes the PINGPONG index to dpu_hw_wb_ops::bind_pingpong_blk() callback and uses separate boolean flag to tell whether WB should be bound or unbound. Simplify this by passing PINGPONG_NONE in case of unbinding and drop the flag completely. Suggested-by:
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Dmitry Baryshkov authored
Currently the driver passes the PINGPONG index to dpu_hw_intf_ops::bind_pingpong_blk() callback and uses separate boolean flag to tell whether INTF should be bound or unbound. Simplify this by passing PINGPONG_NONE in case of unbinding and drop the flag completely. Signed-off-by:
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- 04 Jun, 2023 17 commits
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Neil Armstrong authored
The SM8550 & SM8350 SoC shares the same DP TX IP version, use the SM8350 compatible as fallback for SM8550. Acked-by:
Neil Armstrong <neil.armstrong@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/540552/ Link: https://lore.kernel.org/r/20230601-topic-sm8550-upstream-dp-v2-1-e8778109c757@linaro.orgSigned-off-by:
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Bjorn Andersson authored
The dp_power module keeps track of both the DP controller's struct platform_device and struct device - with the prior pulled out of the dp_parser module. Clean up the duplication by dropping the platform_device reference and just track the passed struct device. Signed-off-by:
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Bjorn Andersson authored
The clk_bulk API already provides error messages indicating which specific clock in the request for which the operation failed, further more these errors are associated with the specific DisplayPort controller (rather than the shared drm_device). The additional error messages int he dp_power module does thereby not provide any benefit. While at it, none of the dp_power handles passed to these functions are dynamic in nature, so there should not be any need for runtime checking them. Drop these as well. Signed-off-by:
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Dmitry Baryshkov authored
Remove most of remains of downstream usbpd code. Mainline kernel uses different approach for managing Type-C / USB-PD, so this remains unused. Signed-off-by:
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Dmitry Baryshkov authored
There is no need to assign a result to temp varable just to return it after a goto. Drop the temporary variable and goto and return the result directly. Reviewed-by:
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Dmitry Baryshkov authored
There is no need to assign a result to temp varable just to return it two lines below. Drop the temporary variable. Reviewed-by:
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Dmitry Baryshkov authored
There is little sense to get intf index just to call dpu_rm_get_intf() on it. Move dpu_rm_get_intf() call to dpu_encoder_get_intf() function. Reviewed-by:
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Dmitry Baryshkov authored
The function dpu_encoder_get_wb() returns controller_id if the corresponding WB is present in the catalog. We can inline this function and rely on dpu_rm_get_wb() returning NULL for indices for which the WB is not present on the device. Reviewed-by:
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Dmitry Baryshkov authored
Remove intf_idx and wb_idx fields from struct dpu_encoder_phys and struct dpu_enc_phys_init_params. Set the hw_intf and hw_wb directly and use them to get the instance index. Reviewed-by:
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Dmitry Baryshkov authored
Move common DPU physical encoder initialization code to the new function dpu_encoder_phys_init(). Reviewed-by:
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Dmitry Baryshkov authored
There is no reason to split the dpu_encoder interface into separate _init() and _setup() phases. Merge them into a single function. Reviewed-by:
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Luca Weiss authored
Add the required config for the v1.1 MDP5 found on MSM8226. Reviewed-by:
Luca Weiss <luca@z3ntu.xyz> Patchwork: https://patchwork.freedesktop.org/patch/540612/ Link: https://lore.kernel.org/r/20230308-msm8226-mdp-v3-4-b6284145d67a@z3ntu.xyzSigned-off-by:
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Luca Weiss authored
Add the compatible for the MDP5 found on MSM8226. Acked-by:
Conor Dooley <conor.dooley@microchip.com> Signed-off-by:
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Luca Weiss authored
MSM8226 uses a modified PLL lock sequence compared to MSM8974, which is based on the function dsi_pll_enable_seq_m in the msm-3.10 kernel. Worth noting that the msm-3.10 downstream kernel also will try other sequences in case this one doesn't work, but during testing it has shown that the _m sequence succeeds first time also: .pll_enable_seqs[0] = dsi_pll_enable_seq_m, .pll_enable_seqs[1] = dsi_pll_enable_seq_m, .pll_enable_seqs[2] = dsi_pll_enable_seq_d, .pll_enable_seqs[3] = dsi_pll_enable_seq_d, .pll_enable_seqs[4] = dsi_pll_enable_seq_f1, .pll_enable_seqs[5] = dsi_pll_enable_seq_c, .pll_enable_seqs[6] = dsi_pll_enable_seq_e, We may need to expand this in the future. Signed-off-by:
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Luca Weiss authored
Add the config for the v1.0.2 DSI found on MSM8226. We can reuse existing bits from other revisions that are identical for v1.0.2. Reviewed-by:
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Luca Weiss authored
Add the compatible for the DSI found on MSM8226. Acked-by:
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Luca Weiss authored
The MSM8226 SoC uses a slightly different 28nm dsi phy. Add a new compatible for it. And while we're at it, in the dsi-phy-28nm.yaml move the 8960 compatible to its correct place so its sorted alphabetically. Acked-by:
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