- 27 Jan, 2018 1 commit
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Stephen Boyd authored
Merge branches 'clk-qcom-alpha-pll', 'clk-check-ops-ptr', 'clk-protect-rate' and 'clk-omap' into clk-next * clk-qcom-alpha-pll: clk: qcom: add read-only alpha pll post divider operations clk: qcom: support for 2 bit PLL post divider clk: qcom: support Brammo type Alpha PLL clk: qcom: support Huayra type Alpha PLL clk: qcom: support for dynamic updating the PLL clk: qcom: support for alpha mode configuration clk: qcom: flag for 64 bit CONFIG_CTL clk: qcom: fix 16 bit alpha support calculation clk: qcom: support for alpha pll properties * clk-check-ops-ptr: clk: check ops pointer on clock register * clk-protect-rate: clk: fix set_rate_range when current rate is out of range clk: add clk_rate_exclusive api clk: cosmetic changes to clk_summary debugfs entry clk: add clock protection mechanism to clk core clk: use round rate to bail out early in set_rate clk: rework calls to round and determine rate callbacks clk: add clk_core_set_phase_nolock function clk: take the prepare lock out of clk_core_set_parent clk: fix incorrect usage of ENOSYS * clk-omap: clk: ti: Drop legacy clk-3xxx-legacy code
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- 21 Dec, 2017 1 commit
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Michael Turquette authored
Merge tag 'omap-for-v4.16/clk-omap3-legacy-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into clk-omap Drop unused omap3 clock data We have been booting omap3 in device tree only mode for a while now, so this is all unused now.
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- 20 Dec, 2017 9 commits
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Jerome Brunet authored
Calling clk_core_set_rate() with core->req_rate is basically a no-op because of the early bail-out mechanism. This may leave the clock in inconsistent state if the rate is out the requested range. Calling clk_core_set_rate() with the closest rate limit could solve the problem but: - The underlying determine_rate() callback needs to account for this corner case (rounding within the range, if possible) - if only round_rate() is available, we rely on luck unfortunately. Fixes: 1c8e6004 ("clk: Add rate constraints to clocks") Tested-by:
Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by:
Michael Turquette <mturquette@baylibre.com> Signed-off-by:
Jerome Brunet <jbrunet@baylibre.com> Signed-off-by:
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Jerome Brunet authored
Using clock rate protection, we can now provide a way for clock consumer to claim exclusive control over the rate of a producer So far, rate change operations have been a "last write wins" affair. This changes allows drivers to explicitly protect against this behavior, if required. Of course, if exclusivity over a producer is claimed more than once, the rate is effectively locked as exclusivity cannot be preempted Tested-by:
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Jerome Brunet authored
clk_summary debugfs entry was already well over the traditional 80 characters per line limit but it grew even larger with the addition of clock protection. clock enable_cnt prepare_cnt protect_cnt rate accuracy phase ---------------------------------------------------------------------------------------------------- wifi32k 1 1 0 32768 0 0 vcpu 0 0 0 2016000000 0 0 xtal 5 5 0 24000000 0 0 This patch reduce the width a bit: enable prepare protect clock count count count rate accuracy phase ---------------------------------------------------------------------------------------- wifi32k 1 1 0 32768 0 0 vcpu 0 0 0 2016000000 0 0 xtal 5 5 0 24000000 0 0 Acked-by:Linus Walleij <linus.walleij@linaro.org> Tested-by:
Quentin Schulz <quentin.schulz@free-electrons.com> Tested-by:
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Jerome Brunet authored
The patch adds clk_core_protect and clk_core_unprotect to the internal CCF API. These functions allow to set a new constraint along the clock tree to prevent any change, even indirect, which may result in rate change or glitch. Tested-by:
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Jerome Brunet authored
The current implementation of clk_core_set_rate_nolock() bails out early if the requested rate is exactly the same as the one set. It should bail out if the request would not result in a rate a change. This is important when the rate is not exactly what is requested, which is fairly common with PLLs. Ex: provider able to give any rate with steps of 100Hz - 1st consumer request 48000Hz and gets it. - 2nd consumer request 48010Hz as well. If we were to perform the usual mechanism, we would get 48000Hz as well. The clock would not change so there is no point performing any checks to make sure the clock can change, we know it won't. This is important to prepare the addition of the clock protection mechanism Acked-by:
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Jerome Brunet authored
Rework the way the callbacks round_rate() and determine_rate() are called. The goal is to do this at a single point and make it easier to add conditions before calling them. Because of this factorization, rate returned by determine_rate() is also checked against the min and max rate values This rework is done to ease the integration of "protected" clock functionality. Acked-by:
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Jerome Brunet authored
Create a core function for set_phase, as it is done for set_rate and set_parent. This rework is done to ease the integration of "protected" clock functionality. Acked-by:
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Jerome Brunet authored
Rework set_parent core function so it can be called when the prepare lock is already held by the caller. This rework is done to ease the integration of the "protected" clock functionality. Acked-by:
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Jerome Brunet authored
ENOSYS is special and should only be used for incorrect syscall number. It does not seem to be the case here. Reported by checkpatch.pl while working on clock protection. Acked-by:
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- 19 Dec, 2017 1 commit
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Jerome Brunet authored
Nothing really prevents a provider from (trying to) register a clock without providing the clock ops structure. We do check the individual fields before using them, but not the structure pointer itself. This may have the usual nasty consequences when the pointer is dereferenced, most likely when checking one the field during the initialization. This is fixed by returning an error on clock register if the ops pointer is NULL. Signed-off-by:
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- 14 Dec, 2017 6 commits
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Tony Lindgren authored
We have now had omap3 booting in device tree only mode for a while and all this code is unused. Acked-by:
Tero Kristo <t-kristo@ti.com> Signed-off-by:
Tony Lindgren <tony@atomide.com>
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Abhishek Sahu authored
Some of the divider settings are preconfigured and should not be changed by the clock framework during frequency change. This patch adds the read-only divider operation for QCOM alpha pll post divider which is equivalent to generic divider operations in 'commit 79c6ab50 ("clk: divider: add CLK_DIVIDER_READ_ONLY flag")'. Signed-off-by:
Abhishek Sahu <absahu@codeaurora.org> Signed-off-by:
Stephen Boyd <sboyd@codeaurora.org>
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Abhishek Sahu authored
Current PLL driver only supports 4 bit PLL post divider so modified the PLL divider operations to support 2 bit PLL post divider. Signed-off-by:
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Abhishek Sahu authored
The Brammo type of Alpha PLL doesn't allow configuration of a VCO, but it does support dynamic update in which the frequency can be changed dynamically without turning off the PLL. Signed-off-by:
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Abhishek Sahu authored
The Huayra type Alpha PLL has a 16 bit alpha value, and depending on the alpha_mode, the alpha value can be treated as M/N value or as a two’s compliment number. This PLL supports dynamic programming. Since the decoding of alpha val and dynamic programming are completely different from other Alpha PLLs we add separate functions for Huayra PLLs. Signed-off-by:
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Abhishek Sahu authored
Some of the Alpha PLLs support dynamic update in which the frequency can be changed dynamically without turning off the PLL. This dynamic update requires the following sequence: 1. Write the desired values to L_VAL and ALPHA_VAL registers 2. Toggle pll_latch_input from low to high 3. Wait for pll_ack_latch to transition from low to high The new L and alpha values have been latched. It may take some time for the PLL to fully settle with these new values. 4. Pull pll_latch_input low Signed-off-by:Rajendra Nayak <rnayak@codeaurora.org> Signed-off-by:
Taniya Das <tdas@codeaurora.org> Signed-off-by:
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- 13 Dec, 2017 4 commits
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Abhishek Sahu authored
The current configuration does not fully configure PLL alpha mode and values so this patch 1. Configures PLL_ALPHA_VAL_U for PLL which supports 40 bit alpha. 2. Adds alpha enable and alpha mode configuration support. Signed-off-by:
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Abhishek Sahu authored
Some of the Alpha PLLs (like Spark and Brammo) don't have a CONFIG_CTL_U register. Add logic to detect when PLLs don't have this second config register and skip programming it during PLL initialization. Signed-off-by:
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Abhishek Sahu authored
The alpha value calculation has been written for 40-bit alpha values which doesn't work work properly for 16-bit ones. The alpha value is calculated on the basis of ALPHA_BITWIDTH to make the computation easy for 40 bit alpha. After calculating the 32 bit alpha, it is converted to 40 bit alpha by making lower bits zero. But if actual alpha register width is less than ALPHA_BITWIDTH, then the actual width can be used for calculation. This also means, during the 40 bit alpha pll set rate path, the lower alpha register is not configured Change the code to calculate the rate and register values from 'alpha_width' instead of hard-coding it so that it can work for the different widths that are supported. Signed-off-by:
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Abhishek Sahu authored
Alpha PLL is a generic name used for QCOM PLLs which uses L and Alpha values for configuring the integer and fractional part. QCOM SoCs use different types of Alpha PLLs for which basic software configuration part is common with following differences. 1. All these PLLs have the same basic registers like PLL_MODE, L_VAL, ALPHA_VAL but some of the register offsets are different between PLLs types. 2. The dynamic programming sequence is different in some of the Alpha PLLs 3. Some of the PLLs don’t have 64 bit config control, 64 bit user control, VCO configuration, etc. Signed-off-by:
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- 07 Dec, 2017 18 commits
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https://github.com/t-kristo/linux-pmStephen Boyd authored
* '4.15-rc1-clkctrl-driver' of https://github.com/t-kristo/linux-pm: (28 commits) clk: ti: omap4: clkctrl data fixes for opt-clocks clk: ti: dm816: add clkctrl clock data dt-bindings: clk: add dm816 clkctrl definitions clk: ti: dm814: add clkctrl clock data dt-bindings: clk: add dm814 clkctrl definitions clk: ti: am43xx: add clkctrl clock data dt-bindings: clk: add am43xx clkctrl definitions clk: ti: am33xx: add clkctrl clock data dt-bindings: clk: add am33xx clkctrl definitions clk: ti: dra7: add clkctrl clock data dt-bindings: clk: add dra7 clkctrl definitions clk: ti: omap5: add clkctrl clock data dt-bindings: clk: add omap5 clkctrl definitions clk: ti: omap3: cleanup unnecessary clock aliases clk: ti: am43xx: cleanup unnecessary clock aliases clk: ti: am33xx: cleanup unnecessary clock aliases clk: ti: dm816x: cleanup unnecessary clock aliases clk: ti: dm814x: cleanup unnecessary clock aliases clk: ti: omap5: cleanup unnecessary clock aliases clk: ti: dra7: drop unnecessary clock aliases ...
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Stephen Boyd authored
* clk-stm32-copyright: clk: stm32-h7: fix copyright
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Benjamin Gaignard authored
Uniformize STMicroelectronics copyrights header Add SPDX identifier Signed-off-by:
Benjamin Gaignard <benjamin.gaignard@st.com> Acked-by:
Alexandre TORGUE <alexandre.torgue@st.com> CC: Gabriel Fernandez <gabriel.fernandez@st.com> Reviewed-by:
Philippe Ombredanne <pombredanne@nexb.com> Acked-by:
Gabriel Fernandez <gabriel.fernandez@st.com> Signed-off-by:
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Stephen Boyd authored
* clk-hi3660-stub: clk: hisilicon: Add support for Hi3660 stub clocks dt-bindings: clk: Hi3660: Document stub clock
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Kaihua Zhong authored
Hi3660 has four stub clocks, which are big and LITTLE cluster clocks, GPU clock and DDR clock. These clocks ask MCU for frequency scaling by sending message through mailbox. This commit adds support for stub clocks, it requests the dedicated mailbox channel at initialization; then later uses this channel to send message to MCU to execute frequency scaling. The four stub clocks share the same mailbox channel, but every stub clock has its own command id so MCU can distinguish the requirement coming for which clock. A shared memory is used to present effective frequency value, so the clock driver uses I/O mapping for the memory and reads back rate value. Reviewed-by:
Leo Yan <leo.yan@linaro.org> Signed-off-by:
Kai Zhao <zhaokai1@hisilicon.com> Signed-off-by:
Tao Wang <kevin.wangtao@hisilicon.com> Signed-off-by:
Ruyi Wang <wangruyi@huawei.com> Signed-off-by:
Kaihua Zhong <zhongkaihua@huawei.com> [sboyd: Fix possible out of bounds access in hi3660_stub_clk_hw_get(), use devm_of_clk_add_hw_provider(), devm_ioremap() returns NULL not error pointers] Signed-off-by:
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Leo Yan authored
Document the DT binding for stub clock which is used for CPU, GPU and DDR frequency scaling. Acked-by:
Rob Herring <robh@kernel.org> Signed-off-by:
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Stephen Boyd authored
* clk-pr-err: clk: h8300: pr_err() strings should end with newlines clk: h8s2678: pr_err() strings should end with newlines SPEAr: clk: pr_err() strings should end with newlines clk: SPEAr: pr_err() strings should end with newlines clk: lpc32xx: pr_err() strings should end with newlines clk: stm32f4: pr_err() strings should end with newlines
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Arvind Yadav authored
pr_err() messages should end with a new-line to avoid other messages being concatenated. Signed-off-by:
Arvind Yadav <arvind.yadav.cs@gmail.com> Signed-off-by:
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Arvind Yadav authored
pr_err() messages should end with a new-line to avoid other messages being concatenated. Signed-off-by:
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Arvind Yadav authored
pr_err() messages should end with a new-line to avoid other messages being concatenated. Signed-off-by:
Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by:
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Arvind Yadav authored
pr_err() messages should end with a new-line to avoid other messages being concatenated. Signed-off-by:
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Arvind Yadav authored
pr_err() messages should end with a new-line to avoid other messages being concatenated. Signed-off-by:
Vladimir Zapolskiy <vz@mleia.com> Signed-off-by:
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Arvind Yadav authored
pr_err() messages should end with a new-line to avoid other messages being concatenated. Signed-off-by:
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Stephen Boyd authored
* clk-qcom-spmi-div: clk: qcom: Add spmi_pmic clock divider support dt-bindings: Add qcom spmi_pmic clock divider bindings
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Stephen Boyd authored
* clk-qcom-audio-fixes: clk: qcom: msm8916: add 12.288 MHz support to codec dig clk clk: qcom: msm8916: fix mnd_width for codec_digcodec clk: qcom: msm8916: Fix i2s clk rates required for mclk
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Srinivas Kandagatla authored
This patch adds 12.288 MHz suport to codec digital clk, this clock. Some external PA requires a 12.288 MHz to work. Signed-off-by:
Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Signed-off-by:
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Srinivas Kandagatla authored
This patch fixes missing mnd_width for codec_digital clk, this is now set to 8 inline with datasheet. Fixes: 3966fab8 ("clk: qcom: Add MSM8916 Global Clock Controller support") Signed-off-by:
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Srinivas Kandagatla authored
lpaif i2s clk rates in the freq table are not accurate enough for I2S mclk. Fix the inaccurate ones and add few more clock rates that are used in LPASS audio driver. Signed-off-by:
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