1. 11 Jul, 2012 1 commit
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    • Bjorn Helgaas's avatar
      Merge branch 'topic/huang-d3cold-v7' into next · 35e7f73c
      Bjorn Helgaas authored
      * topic/huang-d3cold-v7:
        PCI/PM: add PCIe runtime D3cold support
        PCI: do not call pci_set_power_state with PCI_D3cold
        PCI/PM: add runtime PM support to PCIe port
        ACPI/PM: specify lowest allowed state for device sleep state
      35e7f73c
    • Huang Ying's avatar
      PCI/PM: add PCIe runtime D3cold support · 448bd857
      Huang Ying authored
      This patch adds runtime D3cold support and corresponding ACPI platform
      support.  This patch only enables runtime D3cold support; it does not
      enable D3cold support during system suspend/hibernate.
      
      D3cold is the deepest power saving state for a PCIe device, where its main
      power is removed.  While it is in D3cold, you can't access the device at
      all, not even its configuration space (which is still accessible in D3hot).
      Therefore the PCI PM registers can not be used to transition into/out of
      the D3cold state; that must be done by platform logic such as ACPI _PR3.
      
      To support wakeup from D3cold, a system may provide auxiliary power, which
      allows a device to request wakeup using a Beacon or the sideband WAKE#
      signal.  WAKE# is usually connected to platform logic such as ACPI GPE.
      This is quite different from other power saving states, where devices
      request wakeup via a PME message on the PCIe link.
      
      Some devices, such as those in plug-in slots, have no direct platform
      logic.  For example, there is usually no ACPI _PR3 for them.  D3cold
      support for these devices can be done via the PCIe Downstream Port leading
      to the device.  When the PCIe port is powered on/off, the device is powered
      on/off too.  Wakeup events from the device will be notified to the
      corresponding PCIe port.
      
      For more information about PCIe D3cold and corresponding ACPI support,
      please refer to:
      
      - PCI Express Base Specification Revision 2.0
      - Advanced Configuration and Power Interface Specification Revision 5.0
      
      [bhelgaas: changelog]
      Reviewed-by: default avatarRafael J. Wysocki <rjw@sisk.pl>
      Originally-by: default avatarZheng Yan <zheng.z.yan@intel.com>
      Signed-off-by: default avatarHuang Ying <ying.huang@intel.com>
      Signed-off-by: default avatarBjorn Helgaas <bhelgaas@google.com>
      448bd857