- 20 Jan, 2023 40 commits
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Jakub Kicinski authored
Srujana Challa says: ==================== octeontx2-af: Miscellaneous changes for CPT This patchset consists of miscellaneous changes for CPT. - Adds a new mailbox to reset the requested CPT LF. - Modify FLR sequence as per HW team suggested. - Adds support to recover CPT engines when they gets fault. - Updates CPT inbound inline IPsec configuration mailbox, as per new generation of the OcteonTX2 chips. - Adds a new mailbox to return CPT FLT Interrupt info. ==================== Link: https://lore.kernel.org/r/20230118120354.1017961-1-schalla@marvell.comSigned-off-by:
Jakub Kicinski <kuba@kernel.org>
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Srujana Challa authored
CPT HW would trigger the CPT AF FLT interrupt when CPT engines hits some uncorrectable errors and AF is the one which receives the interrupt and recovers the engines. This patch adds a mailbox for CPT VFs to request for CPT faulted and recovered engines info. Signed-off-by:
Srujana Challa <schalla@marvell.com> Signed-off-by:
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Srujana Challa authored
The CN10K CPT coprocessor contains a context processor to accelerate updates to the IPsec security association contexts. The context processor contains a context cache. This patch updates CPT LF ALLOC mailbox to config ctx_ilen requested by VFs. CPT_LF_ALLOC:ctx_ilen is the size of initial context fetch. Signed-off-by:
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Nithin Dabilpuram authored
CN10K CPT coprocessor includes a component named RXC which is responsible for reassembly of inner IP packets. RXC has the feature to evict oldest entries based on age/threshold. The age/threshold is being set to minimum values to evict all entries at the time of teardown. This patch adds code to restore timeout and threshold config after teardown sequence is complete as it is global config. Signed-off-by:
Nithin Dabilpuram <ndabilpuram@marvell.com> Signed-off-by:
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Srujana Challa authored
Optimize CPT PF identification in mbox handling for faster mbox response by doing it at AF driver probe instead of every mbox message. Signed-off-by:
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Srujana Challa authored
On OcteonTX2 platform CPT instruction enqueue is only possible via LMTST operations. The existing FLR sequence mentioned in HRM requires a dummy LMTST to CPT but LMTST can't be submitted from AF driver. So, HW team provided a new sequence to avoid dummy LMTST. This patch adds code for the same. Signed-off-by:
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Srujana Challa authored
On OcteonTX2 SoC, the admin function (AF) is the only one with all priviliges to configure HW and alloc resources, PFs and it's VFs have to request AF via mailbox for all their needs. This patch adds a new mailbox for CPT VFs to request for CPT LF reset. Signed-off-by:
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Srujana Challa authored
When CPT engine has uncorrectable errors, it will get halted and must be disabled and re-enabled. This patch adds code for the same. Signed-off-by:
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Arkadiusz Kubalewski authored
Previously support for GNSS was implemented as a TTY driver, it allowed to access GNSS receiver on /dev/ttyGNSS_<bus><func>. Use generic GNSS subsystem API instead of implementing own TTY driver. The receiver is accessible on /dev/gnss<id>. In case of multiple receivers in the OS, correct device can be found by enumerating either: - /sys/class/net/<eth port>/device/gnss/ - /sys/class/gnss/gnss<id>/device/ Using GNSS subsystem is superior to implementing own TTY driver, as the GNSS subsystem was designed solely for this purpose. It also implements TTY driver but in a common and defined way. From user perspective, there is no difference in communicating with a device, except new path to the device shall be used. The device will provide same information to the userspace as the old one, and can be used in the same way, i.e.: old # gpsmon /dev/ttyGNSS_2100_0 new # gpsmon /dev/gnss0 There is no other impact on userspace tools. User expecting onboard GNSS receiver support is required to enable CONFIG_GNSS=y/m in kernel config. Reviewed-by:
Alexander Lobakin <alexandr.lobakin@intel.com> Signed-off-by:
Karol Kolacinski <karol.kolacinski@intel.com> Signed-off-by:
Michal Michalik <michal.michalik@intel.com> Signed-off-by:
Arkadiusz Kubalewski <arkadiusz.kubalewski@intel.com> Tested-by: Gurucharan G <gurucharanx.g@intel.com> (A Contingent worker at Intel) Signed-off-by:
Tony Nguyen <anthony.l.nguyen@intel.com> Acked-by:
Greg Kroah-Hartman <gregkh@linuxfoundation.org> Signed-off-by:
David S. Miller <davem@davemloft.net>
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Andy Shevchenko authored
The acpi_evaluate_dsm_typed() provides a way to check the type of the object evaluated by _DSM call. Use it instead of open coded variant. Signed-off-by:
Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by:
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Andy Shevchenko authored
When the ACPI part of a driver is optional the methods used in it are expected to be available even if CONFIG_ACPI=n. This is not the case for _DSM related methods. Add stubs for acpi_evaluate_dsm_typed() and acpi_check_dsm() methods. Reported-by:
kernel test robot <lkp@intel.com> Signed-off-by:
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git://git.kernel.org/pub/scm/linux/kernel/git/tnguy/next-queueDavid S. Miller authored
Tony Nguyen says: ==================== Intel Wired LAN Driver Updates 2023-01-19 (ice) This series contains updates to ice driver only. Tsotne and Anatolii implement new handling, and AdminQ command, for firmware LLDP, adding a pending notification to allow for proper cleanup between TC changes. Amritha extends support for drop action outside of switchdev. Siddaraju adjusts restriction for PTP HW clock adjustments. Ani removes an unneeded non-null check and improves reporting of some link modes to utilize more appropriate values. Jesse adds checks to ensure PF VSI type. Przemek combines duplicate checks of the same condition into one check. Tony makes various cleanups to code: removes comments for cppcheck suppressions, reduces scope of some variables, changes some return statements to reflect an explicit 0 return, matches naming for function declaration and definition, adds local variable for readability, and fixes indenting. Sergey separates DDP (Dynamic Device Personalization) code into its own file. ==================== Signed-off-by: -
David S. Miller authored
Daniel Machon says: ==================== net: Introduce new DCB rewrite table There is currently no support for per-port egress mapping of priority to PCP and priority to DSCP. Some support for expressing egress mapping of PCP is supported through ip link, with the 'egress-qos-map', however this command only maps priority to PCP, and for vlan interfaces only. DCB APP already has support for per-port ingress mapping of PCP/DEI, DSCP and a bunch of other stuff. So why not take advantage of this fact, and add a new table that does the reverse. This patch series introduces the new DCB rewrite table. Whereas the DCB APP table deals with ingress mapping of PID (protocol identifier) to priority, the rewrite table deals with egress mapping of priority to PID. It is indeed possible to integrate rewrite in the existing APP table, by introducing new dedicated rewrite selectors, and altering existing functions to treat rewrite entries specially. However, I feel like this is not a good solution, and will pollute the APP namespace. APP is well-defined in IEEE, and some userspace relies of advertised entries - for this fact, separating APP and rewrite into to completely separate objects, seems to me the best solution. The new table shares much functionality with the APP table, and as such, much existing code is reused, or slightly modified, to work for both. ================================================================================ DCB rewrite table in a nutshell ================================================================================ The table is implemented as a simple linked list, and uses the same lock as the APP table. New functions for getting, setting and deleting entries have been added, and these are exported, so they can be used by the stack or drivers. Additionnaly, new dcbnl_setrewr and dcnl_delrewr hooks has been added, to support hardware offload of the entries. ================================================================================ Sparx5 per-port PCP rewrite support ================================================================================ Sparx5 supports PCP egress mapping through two eight-entry switch tables. One table maps QoS class 0-7 to PCP for DE0 (DP levels mapped to drop-eligibility 0) and the other for DE1. DCB does currently not have support for expressing DP/color, so instead, the tagged DEI bit will reflect the DP levels, for any rewrite entries> 7 ('de'). The driver will take apptrust (contributed earlier) into consideration, so that the mapping tables only be used, if PCP is trusted *and* the rewrite table has active mappings, otherwise classified PCP (same as frame PCP) will be used instead. ================================================================================ Sparx5 per-port DSCP rewrite support ================================================================================ Sparx5 support DSCP egress mapping through a single 32-entry table. This table maps classified QoS class and DP level to classified DSCP, and is consulted by the switch Analyzer Classifier at ingress. At egress, the frame DSCP can either be rewritten to classified DSCP to frame DSCP. The driver will take apptrust into consideration, so that the mapping tables only be used, if DSCP is trusted *and* the rewrite table has active mappings, otherwise frame DSCP will be used instead. ================================================================================ Patches ================================================================================ Patch #1 modifies dcb_app_add to work for both APP and rewrite Patch #2 adds dcbnl_app_table_setdel() for setting and deleting both APP and rewrite entries. Patch #3 adds the rewrite table and all required functions, offload hooks and bookkeeping for maintaining it. Patch #4 adds two new helper functions for getting a priority to PCP bitmask map, and a priority to DSCP bitmask map. Patch #5 adds support for PCP rewrite in the Sparx5 driver. Patch #6 adds support for DSCP rewrite in the Sparx5 driver. ================================================================================ v2 -> v3: in dcbnl_ieee_fill() use nla_nest_start() instead of the _noflag() version. Also, cancel the rewrite nest in case of an error (Petr Machata). v1 -> v2: In dcb_setrewr() change proto to u16 as it ought to be, and remove zero initialization of err. (Dan Carpenter). Change name of dcbnl_apprewr_setdel -> dcbnl_app_table_setdel and change the function signature to take a single function pointer. Update uses accordingly (Petr Machata). ==================== Signed-off-by: -
Daniel Machon authored
Add support for DSCP rewrite in Sparx5 driver. On egress DSCP is rewritten from either classified DSCP, or frame DSCP. Classified DSCP is determined by the Analyzer Classifier on ingress, and is mapped from classified QoS class and DP level. Classification of DSCP is by default enabled for all ports. It is required that DSCP is trusted for the egress port *and* rewrite table is not empty, in order to rewrite DSCP based on classified DSCP, otherwise DSCP is always rewritten from frame DSCP. classified_dscp = qos_dscp_map[8 * dp_level + qos_class]; if (active_mappings && dscp_is_trusted) rewritten_dscp = classified_dscp else rewritten_dscp = frame_dscp To rewrite DSCP to 20 for any frames with priority 7: $ dcb apptrust set dev eth0 order dscp $ dcb rewr add dev eth0 7:20 <-- not in iproute2/dcb yet Signed-off-by:
Daniel Machon <daniel.machon@microchip.com> Signed-off-by:
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Daniel Machon authored
Add support for rewrite of PCP and DEI, based on classified Quality of Service (QoS) class and Drop-Precedence (DP) level. The DCB rewrite table is queried for mappings between priority and PCP/DEI. The classified DP level is then encoded in the DEI bit, if a mapping for DEI exists. Sparx5 has four DP levels, where by default, 0 is mapped to DE0 and 1-3 are mapped to DE1. If a mapping exists where DEI=1, then all classified DP levels mapped to DE1 will set the DEI bit. The other way around for DEI=0. Effectively, this means that the tagged DEI bit will reflect the DP level for any mappings where DEI=1. Map priority=1 to PCP=1 and DEI=1: $ dcb rewr add dev eth0 pcp-prio 1:1de Map priority=7 to PCP=2 and DEI=0 $ dcb rewr add dev eth0 pcp-prio 7:2nd Also, sparx5_dcb_ieee_dscp_setdel() has been refactored, to work for both APP and rewrite entries. Signed-off-by:
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Daniel Machon authored
Add two new helper functions to retrieve a mapping of priority to PCP and DSCP bitmasks, where each bitmap contains ones in positions that match a rewrite entry. dcb_ieee_getrewr_prio_dscp_mask_map() reuses the dcb_ieee_app_prio_map, as this struct is already used for a similar mapping in the app table. Signed-off-by:
Petr Machata <petrm@nvidia.com> Signed-off-by:
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Daniel Machon authored
Add new rewrite table and all the required functions, offload hooks and bookkeeping for maintaining it. The rewrite table reuses the app struct, and the entire set of app selectors. As such, some bookeeping code can be shared between the rewrite- and the APP table. New functions for getting, setting and deleting entries has been added. Apart from operating on the rewrite list, these functions do not emit a DCB_APP_EVENT when the list os modified. The new dcb_getrewr does a lookup based on selector and priority and returns the protocol, so that mappings from priority to protocol, for a given selector and ifindex is obtained. Also, a new nested attribute has been added, that encapsulates one or more app structs. This attribute is used to distinguish the two tables. The dcb_lock used for the APP table is reused for the rewrite table. Signed-off-by:
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Daniel Machon authored
In preparation for DCB rewrite. Add a new function for setting and deleting both app and rewrite entries. Moving this into a separate function reduces duplicate code, as both type of entries requires the same set of checks. The function will now iterate through a configurable nested attribute (app or rewrite attr), validate each attribute and call the appropriate set- or delete function. Note that this function always checks for nla_len(attr_itr) < sizeof(struct dcb_app), which was only done in dcbnl_ieee_set and not in dcbnl_ieee_del prior to this patch. This means, that any userspace tool that used to shove in data < sizeof(struct dcb_app) would now receive -ERANGE. Signed-off-by:
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Daniel Machon authored
In preparation to DCB rewrite. Modify dcb_app_add to take new struct list_head * as parameter, to make the used list configurable. This is done to allow reusing the function for adding rewrite entries to the rewrite table, which is introduced in a later patch. Signed-off-by:
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David S. Miller authored
Jerry Ray says: ==================== dsa: lan9303: Move to PHYLINK This patch series moves the lan9303 driver to use the phylink api away from phylib. Migrating to phylink means removing the .adjust_link api. The functionality from the adjust_link is moved to the phylink_mac_link_up api. The code being removed only affected the cpu port. The other ports on the LAN9303 do not need anything from the phylink_mac_link_up api. Patches: 0001 - Whitespace only change aligning the dsa_switch_ops members. No code changes. 0002 - Moves the Turbo bit initialization out of the adjust_link api and places it in a driver initialization execution path. It only needs to be initialized once, it is never changed, and it is not a per-port flag. 0003 - Adds exception handling logic in the extremely unlikely event that the read of the device fails. 0004 - Performance optimization that skips a slow register write if there is no need to perform it. 0005 - Change the way we identify the xMII port as phydev will be NULL when this logic is moved into phylink_mac_link_up. 0006 - Removes adjust_link and begins using the phylink dsa_switch_ops apis. 0007 - Adds XMII port flow control settings in the phylink_mac_link_up() api while cleaning up the ANEG / speed / duplex implementation. --- v6->v7: - Moved the initialization of the Turbo bit into lan9303_setup(). - Added a macro for determining is a port is an XMII port. - Added setting the XMII flow control in the phylink_mac_link_up() API. - removed unnecessary error handling and cleaned up the code flow in phylink_mac_link_up(). v5->v6: - Moved to using port number to identify xMII port for the LAN9303. v4->v5: - Created prep patches to better show how things migrate. - cleaned up comments. v3->v4: - Addressed whitespace issues as a separate patch. - Removed port_max_mtu api patch as it is unrelated to phylink migration. - Reworked the implementation to preserve the adjust_link functionality by including it in the phylink_mac_link_up api. v2->v3: Added back in disabling Turbo Mode on the CPU MII interface. Removed the unnecessary clearing of the phy supported interfaces. v1->v2: corrected the reported mtu size, removing ETH_HLEN and ETH_FCS_LEN ==================== Signed-off-by: -
Jerry Ray authored
While the prior patch moved the adjust_link code into the phylink_mac_link_up api, this patch cleans it up and adds the setting the port's flow control based on the phylink_mac_link_up input parameters. Signed-off-by:
Jerry Ray <jerry.ray@microchip.com> Signed-off-by:
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Jerry Ray authored
This patch replaces the adjust_link api with the phylink apis that provide equivalent functionality. The remaining functionality from the adjust_link is now covered in the phylink_mac_link_up api. Removes: .adjust_link Adds: .phylink_get_caps .phylink_mac_link_up Signed-off-by:
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Jerry Ray authored
In preparing to move the adjust_link logic into the phylink_mac_link_up api, change the macro used to check for the cpu port. In phylink_mac_link_up, the phydev pointer passed in for the CPU port is NULL, so we can't keep using phy_is_pseudo_fixed_link(phydev). Signed-off-by:
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Jerry Ray authored
As the regmap_write() is over a slow bus that will sleep, we can speed up the boot-up time a bit by not bothering to clear a bit that is already clear. Signed-off-by:
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Jerry Ray authored
While it is highly unlikely a read will ever fail, This code fragment is now in a function that allows us to return an error code. A read failure here will cause the lan9303_probe to fail. Signed-off-by:
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Jerry Ray authored
In preparing to remove the .adjust_link api, I am moving the one-time initialization of the device's Turbo Mode bit into a different execution path. This code clears (disables) the Turbo Mode bit which is never used by this driver. Turbo Mode is a non-standard mode that would allow the 100Mbps RMII interface to run at 200Mbps. Signed-off-by:
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Jerry Ray authored
Whitespace preparatory patch, making the dsa_switch_ops table consistent. No code is added or removed. Signed-off-by:
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git://git.kernel.org/pub/scm/linux/kernel/git/saeed/linuxJakub Kicinski authored
Saeed Mahameed says: ==================== mlx5-updates-2023-01-18 1) From Rahul, 1.1) extended range for PTP adjtime and adjphase 1.2) adjphase function to support hardware-only offset control 2) From Roi, code cleanup to the TC module. 3) From Maor, TC support for Geneve and GRE with VF tunnel offload 4) Cleanups and minor updates. * tag 'mlx5-updates-2023-01-18' of git://git.kernel.org/pub/scm/linux/kernel/git/saeed/linux: net/mlx5e: Use read lock for eswitch get callbacks net/mlx5e: Remove redundant allocation of spec in create indirect fwd group net/mlx5e: Support Geneve and GRE with VF tunnel offload net/mlx5: E-Switch, Fix typo for egress net/mlx5e: Warn when destroying mod hdr hash table that is not empty net/mlx5e: TC, Use common function allocating flow mod hdr or encap mod hdr net/mlx5e: TC, Add tc prefix to attach/detach hdr functions net/mlx5e: TC, Pass flow attr to attach/detach mod hdr functions net/mlx5e: Add warning when log WQE size is smaller than log stride size net/mlx5e: Fail with messages when params are not valid for XSK net/mlx5: E-switch, Remove redundant comment about meta rules net/mlx5: Add hardware extended range support for PTP adjtime and adjphase net/mlx5: Add adjphase function to support hardware-only offset control net/mlx5: Suppress error logging on UCTX creation net/mlx5e: Suppress Send WQEBB room warning for PAGE_SIZE >= 16KB ==================== Link: https://lore.kernel.org/r/20230118183602.124323-1-saeed@kernel.orgSigned-off-by:
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Piergiorgio Beruto authored
Coverity reported the following: *** CID 1530573: (UNINIT) drivers/net/phy/phy-c45.c:1036 in genphy_c45_plca_set_cfg() 1030 return ret; 1031 1032 val = ret; 1033 } 1034 1035 if (plca_cfg->node_cnt >= 0) vvv CID 1530573: (UNINIT) vvv Using uninitialized value "val". 1036 val = (val & ~MDIO_OATC14_PLCA_NCNT) | 1037 (plca_cfg->node_cnt << 8); 1038 1039 if (plca_cfg->node_id >= 0) 1040 val = (val & ~MDIO_OATC14_PLCA_ID) | 1041 (plca_cfg->node_id); drivers/net/phy/phy-c45.c:1076 in genphy_c45_plca_set_cfg() 1070 return ret; 1071 1072 val = ret; 1073 } 1074 1075 if (plca_cfg->burst_cnt >= 0) vvv CID 1530573: (UNINIT) vvv Using uninitialized value "val". 1076 val = (val & ~MDIO_OATC14_PLCA_MAXBC) | 1077 (plca_cfg->burst_cnt << 8); 1078 1079 if (plca_cfg->burst_tmr >= 0) 1080 val = (val & ~MDIO_OATC14_PLCA_BTMR) | 1081 (plca_cfg->burst_tmr); This is not actually creating a real problem because the path leading to 'val' being used uninitialized will eventually override the full content of that variable before actually using it for writing the register. However, the fix is simple and comes at basically no cost. Reported-by:
coverity-bot <keescook+coverity-bot@chromium.org> Fixes: 49332341 ("drivers/net/phy: add helpers to get/set PLCA configuration") Signed-off-by:
Piergiorgio Beruto <piergiorgio.beruto@gmail.com> Reviewed-by:
Jacob Keller <jacob.e.keller@intel.com> Link: https://lore.kernel.org/r/f22f1864165a8dbac8b7a2277f341bc8e7a7b70d.1674056765.git.piergiorgio.beruto@gmail.comSigned-off-by:
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Jakub Kicinski authored
Jiri Pirko says: ==================== devlink: linecard and reporters locking cleanup This patchset does not change functionality. Patches 1-2 remove linecards lock and reference counting, converting them to be protected by devlink instance lock as the rest of the objects. Patches 3-4 fix the mlx5 auxiliary device devlink locking scheme whis is needed for proper reporters lock conversion done in the following patches. Patches 5-8 remove reporters locks and reference counting, converting them to be protected by devlink instance lock as the rest of the objects. Patches 9 and 10 convert linecards and reporters dumpit callbacks to recently introduced devlink_nl_instance_iter_dump() infra. Patch 11 removes no longer needed devlink_dump_for_each_instance_get() helper. The last patch adds assertion to devl_is_registered() as dependency on other locks is removed. ==================== Link: https://lore.kernel.org/r/20230118152115.1113149-1-jiri@resnulli.usSigned-off-by:
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Jiri Pirko authored
After region and linecard lock removals, this helper is always supposed to be called with instance lock held. So put the assertion here and remove the comment which is no longer accurate. Signed-off-by:
Jiri Pirko <jiri@nvidia.com> Reviewed-by:
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Jiri Pirko authored
devlink_dump_for_each_instance_get() is currently called from a single place in netlink.c. As there is no need to use this helper anywhere else in the future, remove it and call devlinks_xa_find_get() directly from while loop in devlink_nl_instance_iter_dump(). Also remove redundant idx clear on loop end as it is already done in devlink_nl_instance_iter_dump(). Signed-off-by:
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Jiri Pirko authored
Benefit from recently introduced instance iteration and convert reporters .dumpit generic netlink callback to use it. Signed-off-by:
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Jiri Pirko authored
Benefit from recently introduced instance iteration and convert linecards .dumpit generic netlink callback to use it. Signed-off-by:
Ido Schimmel <idosch@nvidia.com> Reviewed-by:
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Jiri Pirko authored
As long as the reporter life time is protected by devlink instance lock, the reference counting is no longer needed. Remove it. Signed-off-by:
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Jiri Pirko authored
Remove port-specific health reporter destroy function as it is currently the same as the instance one so no longer needed. Inline __devlink_health_reporter_destroy() as it is no longer called from multiple places. Signed-off-by:
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Jiri Pirko authored
Similar to other devlink objects, rely on devlink instance lock and remove object specific reporters_lock. Signed-off-by:
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Jiri Pirko authored
Similar to other devlink objects, protect the reporters list by devlink instance lock. Alongside add unlocked versions of health reporter create/destroy functions and use them in drivers on call paths where the instance lock is held. Signed-off-by:
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Jiri Pirko authored
The MLX5E_LOCKED_FLOW flag is not checked anywhere now so remove it entirely. Signed-off-by:
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Jiri Pirko authored
The fact that devlink instance lock is held over mlx5 auxiliary devices probe and remove routines brought a need to conditionally take devlink instance lock there. The code is checking a MLX5E_LOCKED_FLOW flag in mlx5 priv struct. This is racy and may lead to access devlink objects without holding instance lock or deadlock. To avoid this, the only lock-wise sane solution is to make the devlink entities created by the auxiliary device independent on the original pci devlink instance. Create devlink instance for the auxiliary device and put the uplink port instance there alongside with the port health reporters. Signed-off-by:
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