- 30 Jun, 2023 26 commits
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Emily Deng authored
Need to unpause dpg first, or it will hit follow error during stop dpg: "[drm] Register(1) [regUVD_POWER_STATUS] failed to reach value 0x00000001 != 0x00000000n" Signed-off-by:
Emily Deng <Emily.Deng@amd.com> Reviewed-by:
Leo Liu <leo.liu@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Le Ma authored
Handled in earlier phase Signed-off-by:
Le Ma <le.ma@amd.com> Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
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YiPeng Chai authored
Fatal error occurs in ras poison mode, mode1 reset is used to recover gpu. Signed-off-by:
YiPeng Chai <YiPeng.Chai@amd.com> Reviewed-by:
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Alex Deucher authored
It's required for high priority queues. Link: https://gitlab.freedesktop.org/drm/amd/-/issues/2535Reviewed-and-tested-by:
Jiadong Zhu <Jiadong.Zhu@amd.com> Signed-off-by:
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Alex Deucher authored
So we can selectively enable it on certain devices. No intended functional change. Reviewed-and-tested-by:
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Mario Limonciello authored
PSP functions are already set by psp_early_init() so initializing them a second time is unnecessary. No intended functional changes. Signed-off-by:
Mario Limonciello <mario.limonciello@amd.com> Reviewed-by:
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Mario Limonciello authored
This reverts commit 072030b1. This is no longer necessary when using newer DMUB F/W. Cc: stable@vger.kernel.org Cc: Sean Wang <sean.ns.wang@amd.com> Cc: Marc Rossi <Marc.Rossi@amd.com> Cc: Hamza Mahfooz <Hamza.Mahfooz@amd.com> Cc: Tsung-hua (Ryan) Lin <Tsung-hua.Lin@amd.com> Reviewed-by:
Leo Li <sunpeng.li@amd.com> Signed-off-by:
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Mario Limonciello authored
The same parade TCON issue can potentially happen on Phoenix, and the same PSR resilience changes have been ported into the DMUB firmware. Don't allow running PSR-SU unless on the newer firmware. Cc: stable@vger.kernel.org Cc: Sean Wang <sean.ns.wang@amd.com> Cc: Marc Rossi <Marc.Rossi@amd.com> Cc: Hamza Mahfooz <Hamza.Mahfooz@amd.com> Cc: Tsung-hua (Ryan) Lin <Tsung-hua.Lin@amd.com> Signed-off-by:
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Mario Limonciello authored
A number of parade TCONs are causing system hangs when utilized with older DMUB firmware and PSR-SU. Some changes have been introduced into DMUB firmware to add resilience against these failures. Don't allow running PSR-SU unless on the newer firmware. Cc: stable@vger.kernel.org Cc: Sean Wang <sean.ns.wang@amd.com> Cc: Marc Rossi <Marc.Rossi@amd.com> Cc: Hamza Mahfooz <Hamza.Mahfooz@amd.com> Cc: Tsung-hua (Ryan) Lin <Tsung-hua.Lin@amd.com> Link: https://gitlab.freedesktop.org/drm/amd/-/issues/2443Signed-off-by:
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Mario Limonciello authored
The `DMUB_FW_VERSION` macro has a mistake in that the revision field is off by one byte. The last byte is typically used for other purposes and not a revision. Cc: stable@vger.kernel.org Cc: Sean Wang <sean.ns.wang@amd.com> Cc: Marc Rossi <Marc.Rossi@amd.com> Cc: Hamza Mahfooz <Hamza.Mahfooz@amd.com> Cc: Tsung-hua (Ryan) Lin <Tsung-hua.Lin@amd.com> Reviewed-by:
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Evan Quan authored
The feature mask bit was not correctly cleared. Without that, the L2H and H2L interrupts cannot be enabled. Signed-off-by:
Evan Quan <evan.quan@amd.com> Acked-by:
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Hong-lu Cheng authored
[why] Endless assert caused by LinesInDETChroma=0. [how] Don't floor for LinesInDETChroma=0 Tested-by:
Daniel Wheeler <daniel.wheeler@amd.com> Reviewed-by:
Jun Lei <jun.lei@amd.com> Acked-by:
Rodrigo Siqueira <rodrigo.siqueira@amd.com> Signed-off-by:
Hong-lu Cheng <hong-lu.cheng@amd.com> Signed-off-by:
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Ilya Bakoulin authored
[Why] This display doesn't properly indicate link loss through DPCD bits such as CR_DONE / CHANNEL_EQ_DONE / SYMBOL_LOCKED / INTERLANE_ALIGN_DONE, which all remain set. In addition, DPCD200Eh doesn't match the value of DPCD204h in all cases. For these reasons, we can miss re-training the link, since we don't properly detect link loss with this display. [Why] Add display-specific workaround to read DPCD204h, so that we can detect link loss based on 128b132b-specific status bits in this register. Tested-by:
Wenjing Liu <wenjing.liu@amd.com> Acked-by:
Ilya Bakoulin <ilya.bakoulin@amd.com> Signed-off-by:
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Zhigang Luo authored
port SRIOV VF missed changes from gfx_v9_0 to gfx_v9_4_3. Reviewed-by:
Zhigang Luo <Zhigang.Luo@amd.com> Signed-off-by:
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Mario Limonciello authored
If the securedisplay TA failed to load the first time, it's unlikely to work again after a suspend/resume cycle or reset cycle and it appears to be causing problems in futher attempts. Fixes: e42dfa66 ("drm/amdgpu: Add secure display TA load for Renoir") Reported-by:
Filip Hejsek <filip.hejsek@gmail.com> Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/2633Signed-off-by:
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Mukul Joshi authored
For GFX 9.4.3, interrupt handling needs to be updated for: - Interrupt cookie will have a NodeId field. Each KFD node needs to check the NodeId before processing the interrupt. - For CPX mode, there are additional checks of client ID needed to process the interrupt. - Add NodeId to the process drain interrupt. Signed-off-by:
Mukul Joshi <mukul.joshi@amd.com> Reviewed-by:
Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by:
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Christian König authored
Since adding gang submit we need to take the gang size into account while reserving fences. Signed-off-by:
Christian König <christian.koenig@amd.com> Fixes: 4624459c ("drm/amdgpu: add gang submit frontend v6") Reviewed-by:
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Hamza Mahfooz authored
Currently, it is possible for us to access memory that we shouldn't. Since, we acquire (possibly dangling) pointers to dirty rectangles before doing a bounds check to make sure we can actually accommodate the number of dirty rectangles userspace has requested to fill. This issue is especially evident if a compositor requests both MPO and damage clips at the same time, in which case I have observed a soft-hang. So, to avoid this issue, perform the bounds check before filling a single dirty rectangle and WARN() about it, if it is ever attempted in fill_dc_dirty_rect(). Cc: stable@vger.kernel.org # 6.1+ Fixes: 30ebe415 ("drm/amd/display: add FB_DAMAGE_CLIPS support") Reviewed-by:
Hamza Mahfooz <hamza.mahfooz@amd.com> Signed-off-by:
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Lijo Lazar authored
Publish energy data in 15.625mJ unit for SMU v13.0.6. The same unit is used in Aldebaran also. Signed-off-by:
Lijo Lazar <lijo.lazar@amd.com> Reviewed-by:
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Lijo Lazar authored
Modify it such that it doesn't change the instance mask parameter. Signed-off-by:
Victor Skvortsov <victor.skvortsov@amd.com> Signed-off-by:
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Mangesh Gadre authored
sdma halt/unhalt is performed by psp when frontdoor loading used,so this can be skipped. v2: Instead of removing halt/unhalt completely, driver will do it only during backdoor load. Signed-off-by:Mangesh Gadre <Mangesh.Gadre@amd.com> Reviewed-by:
Asad Kamal <asad.kamal@amd.com> Signed-off-by:
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Tao Zhou authored
No RAS irq is allowed. Signed-off-by:
Tao Zhou <tao.zhou1@amd.com> Reviewed-by:
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Kenneth Feng authored
add abnormal fan detection for smu 13.0.0 Signed-off-by:
Kenneth Feng <kenneth.feng@amd.com> Reviewed-by:
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Xiaogang Chen authored
Since we allow kfd and graphic operate on same GPU VM to have interoperation between them GPU VM may have been used by graphic vm operations before kfd turns a GPU VM into a compute VM. Remove vm clean checking at amdgpu_vm_make_compute. Signed-off-by:
Xiaogang Chen <xiaogang.chen@amd.com> Reviewed-by:
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Mario Limonciello authored
A number of users have reported that there are random hangs occurring caused by PSR-SU specifically on panels that contain the parade 0803 TCON. Users have been able to work around the issue by disabling PSR entirely. To avoid these hangs, disable PSR-SU when this TCON is found. Cc: stable@vger.kernel.org Cc: Sean Wang <sean.ns.wang@amd.com> Cc: Marc Rossi <Marc.Rossi@amd.com> Cc: Hamza Mahfooz <Hamza.Mahfooz@amd.com> Suggested-by:
Tsung-hua (Ryan) Lin <Tsung-hua.Lin@amd.com> Link: https://gitlab.freedesktop.org/drm/amd/-/issues/2443Signed-off-by:
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Mukul Joshi authored
Enable GWS capable queue creation for forward progress gaurantee on GFX 9.4.3. Signed-off-by:
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- 23 Jun, 2023 14 commits
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Evan Quan authored
It is proved that insufficient LC_L1_INACTIVITY setting can cause audio noise on some platform. With the LC_L1_INACTIVITY increased to 4ms, the issue can be resolved. Signed-off-by:
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Aric Cyr authored
This version brings along the following: - DCN314 fixes - DCN32x fixes - New fast update sequence enablement - DC mode clock switching enablement for DCN32x - DP link loss fix - New debugfs entry to set MST link settings Acked-by:
Aric Cyr <aric.cyr@amd.com> Signed-off-by:
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Alvin Lee authored
- DC mode clock switch interface was previously only executed for DCN303. Enable it for DCN32x so that the interface is called correctly - Assign function pointers for DCN32x that are used in the dc mode interface - Update the dc mode interface to work generically for each ASIC - In update_clocks, make sure to consider softmax if we're in DC mode Reviewed-by:
Alvin Lee <alvin.lee2@amd.com> Signed-off-by:
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Ilya Bakoulin authored
[Why] We don't check 128b132b-specific bits in LANE_ALIGN_STATUS_UPDATED DPCD registers when parsing link loss status, which can cause us to miss a link loss notification from some sinks. [How] Add a 128b132b-specific status bit check. Cc: stable@vger.kernel.org # 6.3+ Reviewed-by:
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Dmytro Laktyushkin authored
Correct setting is div by 2 for odm. Seamless odm transitions are enabled with enable_dp_dig_pixel_rate_div_policy debug flag. Fixes: a2c7356f ("drm/amd/display: fix pixel rate update sequence") Reviewed-by:
Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Acked-by:
Dmytro Laktyushkin <dmytro.laktyushkin@amd.com> Signed-off-by:
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Fangzhi Zuo authored
When using debugfs to change MST link settings, we need to wait until the next stream update to apply the preferred link setting. So, trigger a hotplug event right after the preferred link setting is applied. Reviewed-by:
Wayne Lin <wayne.lin@amd.com> Acked-by:
Fangzhi Zuo <jerry.zuo@amd.com> Signed-off-by:
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Leo Chen authored
[Why & How] Having seamless boot on while forcing debug option ODM combine 2 to 1 will cause some corruptions because of some missing programmings. Cc: stable@vger.kernel.org # 6.1+ Reviewed-by:
Leo Chen <sancchen@amd.com> Signed-off-by:
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Austin Zheng authored
Why: Limiting clocks to DC mode max results in some display modes to no longer be supported How: Disable the path that limits the clock values Fixes: 3b718dca ("drm/amd/display: Filter out AC mode frequencies on DC mode systems") Reviewed-by:
Martin Leung <martin.leung@amd.com> Acked-by:
Austin Zheng <austin.zheng@amd.com> Signed-off-by:
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Alvin Lee authored
The new fast update sequence is now supported on some ASICs. So, enable it by default for all applicable ASICs. Reviewed-by:
Samson Tam <samson.tam@amd.com> Acked-by:
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Alvin Lee authored
Clear update flags so the next flip does not have any redundant programming (if a subsequent flip does not have a stream or plane update, the update flags are not cleared). Fixes: 0baae624 ("drm/amd/display: Refactor fast update to use new HWSS build sequence") Reviewed-by:
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Alvin Lee authored
Condition for programming manually trigger used the wrong pipe (always used top pipe instead of the one we are iterating through). Fixes: 0baae624 ("drm/amd/display: Refactor fast update to use new HWSS build sequence") Reviewed-by:
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Sridevi Arvindekar authored
[Why] We are currently missing some ABM registers. [How] Add the missing registers to dce_abm.h. Reviewed-by:
Chris Park <chris.park@amd.com> Acked-by:
Sridevi Arvindekar <sridevi.arvindekar@amd.com> Signed-off-by:
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Austin Zheng authored
Why: Certain display configs resulted in underflow How: Add an entry containing all max DC clock timings Reviewed-by:
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Sung-huai Wang authored
[Why & How] We have to check if stream is properly initialized before calling find_matching_pll(), otherwise we might end up trying to deferecence a NULL pointer. Cc: stable@vger.kernel.org # 6.1+ Reviewed-by:
Sung-huai Wang <danny.wang@amd.com> Signed-off-by:
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