- 08 Jan, 2014 5 commits
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Rongjun Ying authored
USP0 has multiple functions, and has RX and TX frame sync signals, for some scenarios like audio PCM, we don't need both of them. so here we add two possibilities for USP0 only holding one of TX and RX frame sync. Signed-off-by:
Rongjun Ying <Rongjun.Ying@csr.com> Signed-off-by:
Barry Song <Barry.Song@csr.com> Signed-off-by:
Linus Walleij <linus.walleij@linaro.org>
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Bin Shi authored
sdmmc5 has only 3 pins CMD, CLK, DATA which are connected with CSR TriG RF multi-GNSS. The hardware connection is like: DATA -- GPS_SGN CLK -- GPS_RF_CLK CMD -- GPS_MAG here we drop redundant pins in sdmmc5 group. Signed-off-by:
Bin Shi <Bin.Shi@csr.com> Signed-off-by:
Barry Song <Baohua.Song@csr.com> Signed-off-by:
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Qipan Li authored
commit af614b23 adds lost USP-based UART pin groups for prima2, but missed usp1_uart_nostreamctrl group for atlas6, this patch fixes it. this makes USP(Universal Serial Ports) port1 can work as uart without stream ctrl. Signed-off-by:
Qipan Li <Qipan.Li@csr.com> Signed-off-by:
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Chen-Yu Tsai authored
This patch adds the clock output pin functions on the A20. The 2 pins can output a configurable clock to be used by external modules. This is used on the CubieTruck, to supply a 32768 Hz low power clock to the onboard Wifi+BT module. Signed-off-by:
Chen-Yu Tsai <wens@csie.org> Acked-by:
Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by:
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Antonios Vamporakis authored
Signed-off-by:
Antonios Vamporakis <ant@area128.com> CC: John Crispin <blogic@openwrt.org> Signed-off-by:
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- 07 Jan, 2014 4 commits
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Valentine Barshak authored
This adds I2C[0-4] pinmux support to R8A7791 SoC. Signed-off-by:
Valentine Barshak <valentine.barshak@cogentembedded.com> Signed-off-by:
Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by:
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Valentine Barshak authored
This adds VIN[0-2] pinmux support to r8a7791 SoC. VIN1 B mirror is also added along with the primary configuration since it's the only one that provides access to all 24 data bits on VIN1. Signed-off-by:
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Valentine Barshak authored
This groups USB PWEN and OVC pins together on R8A7791 SoC, the same way it's done on R8A7790, since both are needed for a USB device. Signed-off-by:
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Valentine Barshak authored
This fixes a typo in the vin3_sync_mux array (s/VI2/VI3/). Signed-off-by:
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- 20 Dec, 2013 5 commits
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Laurent Pinchart authored
The arrays are never modified, declare them as const. Signed-off-by:
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Laurent Pinchart authored
The arrays are never modified, declare them as const. Signed-off-by:
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Laurent Pinchart authored
The arrays are never modified, make them const. Signed-off-by:
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Laurent Pinchart authored
The enum_ids and var_field_width fields of struct pinmux_data_reg and pinmux_cfg_reg are initialized using compound literals. Cast them to const to store them in .rodata. Signed-off-by:
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Axel Lin authored
Set g->out_bit bit for gpio output high, clear g->out_bit bit for gpio output low. Signed-off-by:
Axel Lin <axel.lin@ingics.com> Signed-off-by:
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- 16 Dec, 2013 8 commits
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Boris BREZILLON authored
Replace the clk_prepare and clk_enable calls by a single clk_prepare_enable call. Signed-off-by:
Boris BREZILLON <b.brezillon@overkiz.com> Acked-by:
Nicolas Ferre <nicolas.ferre@atmel.com> Signed-off-by:
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Boris BREZILLON authored
clk_unprepare shall be called before clk_disable. Fix the issue by replacing the clk_unprepare and clk_disable calls by a single clk_disable_unprepare call. Signed-off-by:
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Sherman Yin authored
This commit adds slew-rate and input-enable/disable support for pinconf -generic. Signed-off-by:
Sherman Yin <syin@broadcom.com> Signed-off-by:
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Bjorn Andersson authored
Use the more specific form 8974 for the compatible to reduce the risk of future mishaps. Signed-off-by:
Bjorn Andersson <bjorn.andersson@sonymobile.com> Signed-off-by:
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Bjorn Andersson authored
Make the bitmaps part of the msm_pinctrl allocation instead of separately allocating them. Signed-off-by:
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Bjorn Andersson authored
Signed-off-by:
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Bjorn Andersson authored
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Bjorn Andersson authored
Add GPIOLIB and OF as dependencies for PINCTRL_MSM8X74, to fix build errors from i386-randconfig. Also add help text and make the entries tristate, while touching these entries. Cc: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by:
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- 13 Dec, 2013 2 commits
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Alexandre Belloni authored
Signed-off-by:
Alexandre Belloni <alexandre.belloni@free-electrons.com> Signed-off-by:
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Alexandre Belloni authored
This allows to get the pin configuration by using debugfs. On my system: # cat /sys/kernel/debug/pinctrl/pinctrl.3/pinconf-pins Signed-off-by:
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- 12 Dec, 2013 11 commits
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Ashwini Ghuge authored
This adds a driver for the Tegra124 pinmux, and required parameterization data for Tegra124. The driver uses the common Tegra pincontrol driver utility functions to implement the majority of the driver. This driver is not compatible with the earlier NVIDIA's SoCs, hence add new compatibile as "nvidia,tegra124-pinmux". Originally written by Ashwini Gguhe. Thierry: - Cleanups in patches. ldewangan: - Fix some entries for groups. - Fix MUX enums and group sequence. Signed-off-by:
Ashwini Ghuge <aghuge@nvidia.com> Signed-off-by:
Laxman Dewangan <ldewangan@nvidia.com> Acked-by:
Stephen Warren <swarren@nvidia.com> Tested-by:
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Laxman Dewangan authored
This device tree binding document describes the Tegra124 pincontrol DT bindings. This document lists all valid properties, names, mux options of Tegra124 pins. Changes from V1: - Referred the dt-binding header file on describing the nodes. Changes from V2: - Rewording reg properties. - drop drv_type as it is not applicable. Signed-off-by:
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Laurent Pinchart authored
On non-DT platforms IRQ controllers associated with the GPIOs have a fixed IRQ base value known at compile time. The sh-pfc driver translates GPIO number to IRQ numbers using a hardcoded table. This mechanism breaks on DT platforms, as the IRQ base values are dynamic in that case. Fix this by specifying IRQs associated with GPIOs in IRQ resources, populated automatically from the device tree. When IRQ resources are specified the driver requires one IRQ resource per GPIO able to generate an interrupt, and uses the translation table to compute the IRQ resource offset instead of the IRQ number. Cc: devicetree@vger.kernel.org Signed-off-by:
Magnus Damm <damm@opensource.se> Signed-off-by:
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Laurent Pinchart authored
There's more than one window, name the field windows. Signed-off-by:
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Laurent Pinchart authored
This makes catching duplicate entries easier. Merge the two IRQ9 entries found after sorting. Signed-off-by:
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Laurent Pinchart authored
The external IRQ15 input multiplexed on GPIO 0 is missing. Add it. Signed-off-by:
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Laurent Pinchart authored
0 is a valid GPIO value, use -1 to terminate the gpios array in IRQ lists. Signed-off-by:
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Laurent Pinchart authored
Some indices take positive values only, make them unsigned. Signed-off-by:
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Alexandre Belloni authored
ops->pin_config_get() is only used in one specific path that will only be taken for generic pinconf drivers (ops->is_generic == true) when dumping the pinconf by using debugfs. By removing the check in pinconf_check_ops(), let's stop pressuring people to write a pin_config_get() function that will never be used and so will probably never be tested. Removing the check in pinconf_pins_show() allows driver to not implement pin_config_get() but still get a dump of the pinconf in debugfs by implementing pin_config_dbg_show(). Finally, not implementing pin_config_get() now results in returning -ENOTSUPP instead of -EINVAL. While this doesn't have any real impact for now, this feels more right. Signed-off-by:
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Alexandre Belloni authored
When passing a not initialized config parameter, at91_pinconf_get() would return a bogus value. Fix that by initializing it to zero before using it. Signed-off-by:
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Alexandre Belloni authored
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- 11 Dec, 2013 2 commits
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Linus Walleij authored
We had a compilation failure on x86_64 due to missing OF support as this was an implicit dependency. Add an explicit dependency on OF and OF_IRQ on the SoC driver. Cc: Bjorn Andersson <bjorn.andersson@sonymobile.com> Signed-off-by:
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- 10 Dec, 2013 3 commits
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Valentine Barshak authored
There are VIN2 and VIN3 channels available on the R8A7790 SoC. VIN2 supports 4/8/16/18/24-bit data, while VIN3 supports 8-bit. Add both here, covering all possible data pin configurations. Signed-off-by:
Laurent Pinchart <laurent.pinchart@ideasonboard.com>
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Valentine Barshak authored
Both VIN0 and VIN1 channels support identical input interfaces. Add missing VIN1 pins here and organize them in the same pin groups as VIN0. Signed-off-by:
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Valentine Barshak authored
This reorganizes and renames VIN0 data pin groups to cover all possible configurations. There's total of eight data pin groups, one per each configuration. Most of the groups share the same pin/mux array. Only the 18-bit configuration needs a separate pin/mux array since in combines interleaved data pins. Signed-off-by:
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