- 19 Apr, 2018 2 commits
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Rex Zhu authored
Make sure to update the MCLK and SCLK flags when setting the VDDC flags due to dependencies. Reviewed-by:
Alex Deucher <alexander.deucher@amd.com> Signed-off-by:
Rex Zhu <Rex.Zhu@amd.com> Signed-off-by:
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Harry Wentland authored
Even though this is required for degamma since DCE HW only supports a couple predefined LUTs we can just program the LUT directly for regamma. This fixes dark screens which occurs when we program regamma to bypass while degamma is using srgb LUT. Signed-off-by:
Harry Wentland <harry.wentland@amd.com> Reviewed-by:
Leo Li <sunpeng.li@amd.com> Cc: stable@vger.kernel.org Signed-off-by:
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- 12 Apr, 2018 7 commits
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git://people.freedesktop.org/~agd5f/linuxDave Airlie authored
- Add a PX quirk for radeon - Fix flickering and stability issues with DC on some platforms - Fix HDMI audio regression - Few other misc DC and base driver fixes * 'drm-next-4.17' of git://people.freedesktop.org/~agd5f/linux: Revert "drm/amd/display: disable CRTCs with NULL FB on their primary plane (V2)" Revert "drm/amd/display: fix dereferencing possible ERR_PTR()" drm/amd/display: Fix regamma not affecting full-intensity color values drm/amd/display: Fix FBC text console corruption drm/amd/display: Only register backlight device if embedded panel connected drm/amd/display: fix brightness level after resume from suspend drm/amd/display: HDMI has no sound after Panel power off/on drm/amdgpu: add MP1 and THM hw ip base reg offset drm/amdgpu: fix null pointer panic with direct fw loading on gpu reset drm/radeon: add PX quirk for Asus K73TK
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Dave Airlie authored
Merge tag 'drm-misc-next-fixes-2018-04-11' of git://anongit.freedesktop.org/drm/drm-misc into drm-next omap: Fix crash on AM4 EVM, and all OMAP2/3 boards (Tomi) Cc: Tomi Valkeinen <tomi.valkeinen@ti.com> * tag 'drm-misc-next-fixes-2018-04-11' of git://anongit.freedesktop.org/drm/drm-misc: drm/omap: fix crash if there's no video PLL
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Harry Wentland authored
This seems to cause flickering and lock-ups for a wide range of users. Revert until we've found a proper fix for the flickering and lock-ups. This reverts commit 36cc549d. Cc: Shirish S <shirish.s@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org Reviewed-by:
Michel Dänzer <michel.daenzer@amd.com> Signed-off-by:
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Harry Wentland authored
This reverts commit cd2d6c92. Cc: Shirish S <shirish.s@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org Reviewed-by:
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Leo (Sunpeng) Li authored
Hardware understands the regamma LUT as a piecewise linear function, with points spaced exponentially along the range. We previously programmed the LUT for range [2^-10, 2^0). This causes (normalized) color values of 1 (=2^0) to miss the programmed LUT, and fall onto the end region. For DCE, the end region is extrapolated using a single (base, slope) pair, using the max y-value from the last point in the curve as base. This presents a problem, since this value affects all three color channels. Scaling down the intensity of say - the blue regamma curve - will not affect it's end region. This is especially noticiable when using RedShift. It scales down the blue and green channels, but leaves full-intensity colors unshifted. Therefore, extend the range to cover [2^-10, 2^1) by programming another hardware segment, containing only one point. That way, we won't be hitting the end region. Note that things are a bit different for DCN, since the end region can be set per-channel. Signed-off-by:
Krunoslav Kovac <Krunoslav.Kovac@amd.com> Acked-by:
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Roman Li authored
Signed-off-by:
Roman Li <roman.li@amd.com> Reviewed-by:
Charlene Liu <Charlene.Liu@amd.com> Acked-by:
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Harry Wentland authored
Signed-off-by:
Tony Cheng <Tony.Cheng@amd.com> Acked-by:
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- 11 Apr, 2018 5 commits
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Roman Li authored
Adding missing call to cache current backlight values. Otherwise the brightness resets to default value on resume. Signed-off-by:
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Charlene Liu authored
Signed-off-by:
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Evan Quan authored
Signed-off-by:
Evan Quan <evan.quan@amd.com> Reviewed-by:
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Huang Rui authored
When system uses fw direct loading, then psp context structure won't be initiliazed. And it is also unable to execute mode reset. [ 434.601474] amdgpu 0000:0c:00.0: GPU reset begin! [ 434.694326] amdgpu 0000:0c:00.0: GPU reset [ 434.743152] BUG: unable to handle kernel NULL pointer dereference at 0000000000000058 [ 434.838474] IP: psp_gpu_reset+0xc/0x30 [amdgpu] [ 434.893532] PGD 406ed9067 [ 434.893533] P4D 406ed9067 [ 434.926376] PUD 400b46067 [ 434.959217] PMD 0 [ 435.033379] Oops: 0000 [#1] SMP [ 435.072573] Modules linked in: amdgpu(OE) chash(OE) gpu_sched(OE) ttm(OE) drm_kms_helper(OE) drm(OE) fb_sys_fops syscopyarea sysfillrect sysimgblt rpcsec_gss_krb5 auth_rpcgss nfsv4 nfs lockd grace fscache snd_hda_codec_realtek snd_hda_codec_generic snd_hda_codec_hdmi snd_hda_intel snd_hda_codec snd_hda_core snd_hwdep snd_pcm edac_mce_amd snd_seq_midi snd_seq_midi_event kvm_amd snd_rawmidi kvm irqbypass crct10dif_pclmul crc32_pclmul snd_seq ghash_clmulni_intel snd_seq_device pcbc snd_timer eeepc_wmi aesni_intel snd asus_wmi aes_x86_64 sparse_keymap crypto_simd glue_helper joydev soundcore wmi_bmof cryptd video i2c_piix4 shpchp 8250_dw i2c_designware_platform mac_hid i2c_designware_core sunrpc parport_pc ppdev lp parport autofs4 hid_generic igb usbhid dca ptp mxm_wmi pps_core ahci hid i2c_algo_bit [ 435.931754] libahci wmi Signed-off-by:
Huang Rui <ray.huang@amd.com> Reviewed-by:
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Nico Sneck authored
With this the dGPU turns on correctly. Signed-off-by:
Nico Sneck <nicosneck@hotmail.com> Signed-off-by:
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- 10 Apr, 2018 2 commits
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git://people.freedesktop.org/~agd5f/linuxDave Airlie authored
A few fixes for 4.17: - Fix a potential use after free in a error case - Fix pcie lane handling in amdgpu SI dpm - sdma pipeline sync fix - A few vega12 cleanups and fixes - Misc other fixes * 'drm-next-4.17' of git://people.freedesktop.org/~agd5f/linux: drm/amdgpu: Fix memory leaks at amdgpu_init() error path drm/amdgpu: Fix PCIe lane width calculation drm/radeon: Fix PCIe lane width calculation drm/amdgpu/si: implement get/set pcie_lanes asic callback drm/amdgpu: Add support for SRBM selection v3 Revert "drm/amdgpu: Don't change preferred domian when fallback GTT v5" drm/amd/powerply: fix power reading on Fiji drm/amd/powerplay: Enable ACG SS feature drm/amdgpu/sdma: fix mask in emit_pipeline_sync drm/amdgpu: Fix KIQ hang on bare metal for device unbind/bind back v2. drm/amd/pp: Clean header file in vega12_smumgr.c drm/amd/pp: Remove Dead functions on Vega12 drm/amd/pp: silence a static checker warning drm/amdgpu: drop compute ring timeout setting for non-sriov only (v2) drm/amdgpu: fix typo of domain fallback
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Dave Airlie authored
Merge tag 'drm-misc-next-fixes-2018-04-04' of git://anongit.freedesktop.org/drm/drm-misc into drm-next hda_intel: Don't declare azx PM ops if VGA_SWITCHEROO configured (Lukas) Cc: Lukas Wunner <lukas@wunner.de> Cc: Takashi Iwai <tiwai@suse.de> * tag 'drm-misc-next-fixes-2018-04-04' of git://anongit.freedesktop.org/drm/drm-misc: ALSA: hda - Silence PM ops build warning
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- 05 Apr, 2018 1 commit
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Tomi Valkeinen authored
Commit 8a7eda76 ("drm: omapdrm: dispc: Pass DISPC pointer to remaining dispc API functions") made dpi.c use ctx->pll even when there's no PLL, causing a crash at modeset on AM4 EVM, and presumably all OMAP2/3 boards. Fix this by having struct dpi_data pointer in the ctx instead, giving access to dispc without going through the pll. Fixes: 8a7eda76 ("drm: omapdrm: dispc: Pass DISPC pointer to remaining dispc API functions") Signed-off-by:
Tomi Valkeinen <tomi.valkeinen@ti.com> Reported-by:
Keerthy <j-keerthy@ti.com> Cc: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Tested-by:
Laurent Pinchart <laurent.pinchart@ideasonboard.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180405065537.29818-1-tomi.valkeinen@ti.com
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- 03 Apr, 2018 15 commits
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Takashi Iwai authored
amdgpu driver checks vgacon_text_force() after some initializations but without cleaning up. This will result in leaks. Move the check of vgacon_text_force() to the beginning of amdgpu_init() for fixing it and also for optimization. Signed-off-by:
Takashi Iwai <tiwai@suse.de> Signed-off-by:
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Alex Deucher authored
The calculation of the lane widths via ATOM_PPLIB_PCIE_LINK_WIDTH_MASK and ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT macros did not increment the resulting value, per the comment in pptable.h ("lanes - 1"), and per usage elsewhere. Port of the radeon fix to amdgpu. Acked-by:Christian König <christian.koenig@amd.com> Acked-by:
Chunming Zhou <david1.zhou@amd.com> Bug: https://bugs.freedesktop.org/show_bug.cgi?id=102553Signed-off-by:
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Paul Parsons authored
Two years ago I tried an AMD Radeon E8860 embedded GPU with the drm driver. The dmesg output included driver warnings about an invalid PCIe lane width. Tracking the problem back led to si_set_pcie_lane_width_in_smc(). The calculation of the lane widths via ATOM_PPLIB_PCIE_LINK_WIDTH_MASK and ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT macros did not increment the resulting value, per the comment in pptable.h ("lanes - 1"), and per usage elsewhere. Applying the increment silenced the warnings. The code has not changed since, so either my analysis was incorrect or the bug has gone unnoticed. Hence submitting this as an RFC. Acked-by:Paul Parsons <lost.distance@yahoo.com> Signed-off-by:
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Alex Deucher authored
Required for dpm setup on some asics. Fixes a NULL dereference on asics that require it. Acked-by:
Abel Garcia Dorta <mercuriete@yahoo.es> Signed-off-by:
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Andrey Grodzovsky authored
Also remove code duplication in write and read regs functions. This also fixes potential missing unlock in amdgpu_debugfs_regs_write in case get_user would fail. v2: Add SRBM mutex locking. v3: Fix TO counter and fix comment location. Signed-off-by:
Andrey Grodzovsky <andrey.grodzovsky@amd.com> Reviewed-by:
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Chunming Zhou authored
This reverts commit bbaf1871ea1d7b7021e350a3e8bb1ec8408c2030. Felix reports this commit causes regression. Signed-off-by:
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Eric Huang authored
Power value is wrong reported by customer. It is a regression by commit a7c7bc4c Author: Rex Zhu <Rex.Zhu@amd.com> Date: Mon Mar 27 15:32:59 2017 +0800 drm/amd/powerplay: reduce sample period time for power readings. Signed-off-by:
Eric Huang <JinHuiEric.Huang@amd.com> Acked-by:
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Kenneth Feng authored
Port the atomfirmware.h and populates the updated pptable to SMU.With the new parameters in the new pptable, the ACG SS feature is enabled. Signed-off-by:
Kenneth Feng <kenneth.feng@amd.com> Reviewed-by:
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Alex Deucher authored
Needs to be a 32 bit mask. Acked-by:
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Andrey Grodzovsky authored
Problem: When unbind and then bind back the device KIQ hangs on Vega after mapping KCQs request. Fix: Adding deinitialzie code from CAIL during HW fini solves the hang. v2: use srbm_mutex around soc15_grbm_select() Signed-off-by:
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Rex Zhu authored
Reviewed-by:
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Rex Zhu authored
Remove Vega12 DIDT config functions. Reviewed-by:
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Dan Carpenter authored
This has a static checker warning because "frev" and "crev" can be uninitialized if "info" is NULL. I just changed the order of the checks so that we check "info" first. Reviewed-by:
Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by:
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Evan Quan authored
Sriov still wants these error messags on timeout. So, for sriov use case, the timeout setting on compute rings is kept. -v2: clean the code Signed-off-by:
Monk Liu <monk.liu@amd.com> Signed-off-by:
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Chunming Zhou authored
Signed-off-by:
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- 29 Mar, 2018 1 commit
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Lukas Wunner authored
The system sleep PM ops azx_suspend() and azx_resume() were previously called by vga_switcheroo, but commit 07f4f97d ("vga_switcheroo: Use device link for HDA controller") removed their invocation. Unfortunately the commit neglected to update the #ifdef surrounding the two functions, so if CONFIG_PM_SLEEP is *not* enabled but all three of CONFIG_PM, CONFIG_VGA_SWITCHEROO and CONFIG_SND_HDA_CODEC_HDMI *are* enabled, the compiler now emits the following warning: sound/pci/hda/hda_intel.c:1024:12: warning: 'azx_resume' defined but not used [-Wunused-function] static int azx_resume(struct device *dev) ^~~~~~~~~~ sound/pci/hda/hda_intel.c:989:12: warning: 'azx_suspend' defined but not used [-Wunused-function] static int azx_suspend(struct device *dev) ^~~~~~~~~~~ Silence by updating the #ifdef. Because the #ifdef block now uses the same condition as the one immediately succeeding it, the two blocks can be collapsed together, shaving off another two lines. Fixes: 07f4f97d ("vga_switcheroo: Use device link for HDA controller") Reviewed-by:
Arnd Bergmann <arnd@arndb.de> Signed-off-by:
Lukas Wunner <lukas@wunner.de> Link: https://patchwork.kernel.org/patch/10313441/ Link: https://patchwork.freedesktop.org/patch/msgid/b8e70e34a9acbd4f0a1a6c7673cea96888ae9503.1522323444.git.lukas@wunner.de
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- 28 Mar, 2018 4 commits
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git://anongit.freedesktop.org/drm/drm-miscDave Airlie authored
- Mask mode type garbage from userspace (Ville) Something went wrong on the misc tree side, but I'll pull the patch directly. * 'drm-misc-next-fixes' of git://anongit.freedesktop.org/drm/drm-misc: drm: Fix uabi regression by allowing garbage mode->type from userspace
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git://people.freedesktop.org/~gabbayo/linuxDave Airlie authored
- GPUVM support for dGPUs - KFD events support for dGPUs - Fix live-lock situation when restoring multiple evicted processes - Fix VM page table allocation on large-bar systems - Fix for build failure on frv architecture * tag 'drm-amdkfd-next-2018-03-27' of git://people.freedesktop.org/~gabbayo/linux: drm/amdkfd: Use ordered workqueue to restore processes drm/amdgpu: Fix acquiring VM on large-BAR systems drm/amdkfd: Add module option for testing large-BAR functionality drm/amdkfd: Kmap event page for dGPUs drm/amdkfd: Add ioctls for GPUVM memory management drm/amdkfd: Add TC flush on VMID deallocation for Hawaii drm/amdkfd: Allocate CWSR trap handler memory for dGPUs drm/amdkfd: Add per-process IDR for buffer handles drm/amdkfd: Aperture setup for dGPUs drm/amdkfd: Remove limit on number of GPUs drm/amdkfd: Populate DRM render device minor drm/amdkfd: Create KFD VMs on demand drm/amdgpu: Add kfd2kgd interface to acquire an existing VM drm/amdgpu: Add helper to turn an existing VM into a compute VM drm/amdgpu: Fix initial validation of PD BO for KFD VMs drm/amdgpu: Move KFD-specific fields into struct amdgpu_vm drm/amdkfd: fix uninitialized variable use drm/amdkfd: add missing include of mm.h
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Dave Airlie authored
Merge tag 'drm-intel-next-fixes-2018-03-27' of git://anongit.freedesktop.org/drm/drm-intel into drm-next - Display fixes for booting with MST hub lid closed and display freezing after hibernation (fd.o bugs 105470 & 105196) - Fix for a very rare interrupt handling race resulting in GPU hang * tag 'drm-intel-next-fixes-2018-03-27' of git://anongit.freedesktop.org/drm/drm-intel: drm/i915: Fix hibernation with ACPI S0 target state drm/i915/execlists: Use a locked clear_bit() for synchronisation with interrupt drm/i915: Specify which engines to reset following semaphore/event lockups drm/i915/dp: Write to SET_POWER dpcd to enable MST hub.
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Dave Airlie authored
Linux 4.16-rc7 This was requested by Daniel, and things were getting a bit hard to reconcile, most of the conflicts were trivial though.
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- 27 Mar, 2018 3 commits
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Imre Deak authored
After commit dd9f31c7 Author: Imre Deak <imre.deak@intel.com> Date: Wed Aug 16 17:46:07 2017 +0300 drm/i915/gen9+: Set same power state before hibernation image save/restore during hibernation/suspend the power domain functionality got disabled, after which resume could leave it incorrectly disabled if the ACPI target state was S0 during suspend and i915 was not loaded by the loader kernel. This was caused by not considering if we resumed from hibernation as the condition for power domains reiniting. Fix this by simply tracking if we suspended power domains during system suspend and reinit power domains accordingly during resume. This will result in reiniting power domains always when resuming from hibernation, regardless of the platform and whether or not i915 is loaded by the loader kernel. The reason we didn't catch this earlier is that the enabled/disabled state of power domains during PMSG_FREEZE/PMSG_QUIESCE is platform and kernel config dependent: on my SKL the target state is S4 during PMSG_FREEZE and (with the driver loaded in the loader kernel) S0 during PMSG_QUIESCE. On the reporter's machine it's S0 during PMSG_FREEZE but (contrary to this) power domains are not initialized during PMSG_QUIESCE since i915 is not loaded in the loader kernel, or it's loaded but without the DMC firmware being available. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105196 Reported-and-tested-by: amn-bas@hotmail.com Fixes: dd9f31c7 ("drm/i915/gen9+: Set same power state before hibernation image save/restore") Cc: amn-bas@hotmail.com Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: <stable@vger.kernel.org> Signed-off-by:
Imre Deak <imre.deak@intel.com> Reviewed-by:
Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180322143642.26883-1-imre.deak@intel.com (cherry picked from commit 0f90603c) Signed-off-by:
Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
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Chris Wilson authored
We were relying on the uncached reads when processing the CSB to provide ourselves with the serialisation with the interrupt handler (so we could detect new interrupts in the middle of processing the old one). However, in commit 767a983a ("drm/i915/execlists: Read the context-status HEAD from the HWSP") those uncached reads were eliminated (on one path at least) and along with them our serialisation. The result is that we would very rarely miss notification of a new interrupt and leave a context-switch unprocessed, hanging the GPU. Fixes: 767a983a ("drm/i915/execlists: Read the context-status HEAD from the HWSP") Signed-off-by:
Chris Wilson <chris@chris-wilson.co.uk> Cc: Michel Thierry <michel.thierry@intel.com> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Cc: Mika Kuoppala <mika.kuoppala@intel.com> Reviewed-by:
Tvrtko Ursulin <tvrtko.ursulin@intel.com> Reviewed-by:
Mika Kuoppala <mika.kuoppala@linux.intel.com> Reviewed-by:
Michel Thierry <michel.thierry@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180321091027.21034-1-chris@chris-wilson.co.uk (cherry picked from commit 9153e6b7) Signed-off-by:
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Chris Wilson authored
If the GPU is stuck waiting for an event or for a semaphore, we need to reset the GPU in order to recover. We have to tell the reset routine which engines we want reset, but we were still using the old interface and declaring it as "not-fatal". Fixes: 14b730fc ("drm/i915/tdr: Prepare error handler to accept mask of hung engines") Signed-off-by:
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