- 18 Mar, 2024 5 commits
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Konrad Dybcio authored
Killing the platform with a single write and no firmware involvement is pretty cool, add support for it. Note that due to restart notifier priority settings, PSCI reset will be used instead, unless: a) PSCI is not exposed by the firmware (e.g. because the fw was replaced) or b) PSCI restart fails for some reason Signed-off-by:
Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20240307-topic-8280_nodes-v1-3-4eba20e08902@linaro.orgSigned-off-by:
Bjorn Andersson <andersson@kernel.org>
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Konrad Dybcio authored
Describe the QFPROM NVMEM block. Also, add a subnode to represent the GPU speed bin region within it. Signed-off-by:
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Jianhua Lu authored
Add usb pd negotiation, but charging is controlled by pm8150b pmic, so it can only charge battery with 5W, Signed-off-by:
Jianhua Lu <lujianhua000@gmail.com> Link: https://lore.kernel.org/r/20240302131025.13741-1-lujianhua000@gmail.comSigned-off-by:
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Johan Hovold authored
The DWC PCIe controller can be used with its internal MSI controller or with an external one such as the GICv3 Interrupt Translation Service (ITS). Add the msi-map properties needed to use the GIC ITS. This will also make Linux switch to the ITS implementation, which allows for assigning affinity to individual MSIs. Note that using the GIC ITS on SC8280XP will cause Advanced Error Reporting (AER) interrupts to be received on errors unlike when using the internal MSI controller. This will specifically lead to notifications about Correctable Errors being logged for the Wi-Fi controller on the Lenovo ThinkPad X13s when ASPM L0s is enabled. Suggested-by:
Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Reviewed-by:
Johan Hovold <johan+linaro@kernel.org> Link: https://lore.kernel.org/r/20240306095651.4551-6-johan+linaro@kernel.orgSigned-off-by:
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Johan Hovold authored
Add the missing PCIe CX performance level votes to avoid relying on other drivers (e.g. USB or UFS) to maintain the nominal performance level required for Gen3 speeds. Fixes: 813e8315 ("arm64: dts: qcom: sc8280xp/sa8540p: add PCIe2-4 nodes") Cc: stable@vger.kernel.org # 6.2 Reviewed-by:
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- 17 Mar, 2024 2 commits
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Konrad Dybcio authored
Hook up the interrupts that signal the Limits Management Hardware has started some sort of throttling action. In testing, you may notice the A78C cluster throttle IRQ fire count stays at zero. After an hour of painful experiments on an X13s, I was able to get that cluster to heat up near 90 degC, after which the IRQ has indeed fired. So it stands to reason that the heat output difference between the A78C and X1C clusters is so massive that LMH rarely decides to throttle the "little" one based on its power metrics. Fixes: 152d1faf ("arm64: dts: qcom: add SC8280XP platform") Signed-off-by:
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Ritesh Kumar authored
Enable Display Subsystem with Novatek NT36672E Panel on qcm6490 idp platform. Signed-off-by:
Ritesh Kumar <quic_riteshk@quicinc.com> Reviewed-by:
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20240215103929.19357-3-quic_riteshk@quicinc.comSigned-off-by:
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- 04 Mar, 2024 3 commits
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Jianhua Lu authored
Xiaomi Pad 5 Pro has a 2560x1600 portrait screen, set RIGHT_UP rotation to make it look like a landscape screen. Signed-off-by:
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Abel Vesa authored
The actual size of the channels registers region is 4MB, according to the documentation. This issue was not caught until now because the driver was supposed to allow same regions being mapped multiple times for supporting multiple buses. Thie driver is using platform_get_resource_byname() and devm_ioremap() towards that purpose, which intentionally avoids devm_request_mem_region() altogether. Fixes: 10e02467 ("arm64: dts: qcom: sm8650: add interconnect dependent device nodes") Reviewed-by:
Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by:
Abel Vesa <abel.vesa@linaro.org> Reviewed-by:
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Abel Vesa authored
The actual size of the channels registers region is 4MB, according to the documentation. This issue was not caught until now because the driver was supposed to allow same regions being mapped multiple times for supporting multiple buses. Thie driver is using platform_get_resource_byname() and devm_ioremap() towards that purpose, which intentionally avoids devm_request_mem_region() altogether. Fixes: ffc50b2d ("arm64: dts: qcom: Add base SM8550 dtsi") Reviewed-by:
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- 20 Feb, 2024 1 commit
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Dmitry Baryshkov authored
The patch adding Type-C support for sm6115 was misapplied. All the orientation switch configuration ended up at the UFS PHY node instead of the USB PHY node. Move the data bits to the correct place. Fixes: a06a2f12 ("arm64: dts: qcom: qrb4210-rb2: enable USB-C port handling") Signed-off-by:
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- 19 Feb, 2024 3 commits
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Manivannan Sadhasivam authored
"msi-map-mask" is a required property for all Qcom PCIe controllers as it would allow all PCIe devices under a bus to share the same MSI identifier. Without this property, each device has to use a separate MSI identifier which is not possible due to platform limitations. Currently, this is not an issue since only one device is connected to the bus on boards making use of this SoC. Fixes: a33a532b ("arm64: dts: qcom: sm8650: Use GIC-ITS for PCIe0 and PCIe1") Signed-off-by:
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20240216-sm8550-msi-map-fix-v1-1-b66d83ce48b7@linaro.orgSigned-off-by:
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Krzysztof Kozlowski authored
Underscores should not be used in node names (dtc with W=2 warns about them), so replace them with hyphens. Signed-off-by:
Douglas Anderson <dianders@chromium.org> Link: https://lore.kernel.org/r/20240213145124.342514-1-krzysztof.kozlowski@linaro.orgSigned-off-by:
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Stefan Hansson authored
This documents Samsung Galaxy Tab 4 10.1 LTE (samsung,matisselte) which is a tablet by Samsung based on the MSM8926 SoC. Signed-off-by:
Stefan Hansson <newbyte@postmarketos.org> Reviewed-by:
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- 17 Feb, 2024 1 commit
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Dmitry Baryshkov authored
Define VBUS regulator and the Type-C handling block as present on the Quacomm PM4125 PMIC. Reviewed-by:
Bryan O'Donoghue <bryan.odonoghue@linaro.org> Link: https://lore.kernel.org/r/20240202-pm4125-typec-v2-3-12771d85700d@linaro.orgSigned-off-by:
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- 16 Feb, 2024 11 commits
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Lucas Karpinski authored
pcie2a and pcie3a both cause interrupt storms to occur. However, when both are enabled simultaneously, the two combined interrupt storms will lead to rcu stalls. Red Hat is the only company still using this board and since we still need pcie3a, just disable pcie2a. Signed-off-by:
Lucas Karpinski <lkarpins@redhat.com> Reviewed-by:
Brian Masney <bmasney@redhat.com> Link: https://lore.kernel.org/r/qcoqksikfvdqxk6stezbzc7l2br37ccgqswztzqejmhrkhbrwt@ta4npsm35mqkSigned-off-by:
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Viken Dadhaniya authored
Populate the DTSI node for slimbus instance to be used by bluetooth FM audio case. Signed-off-by:
Viken Dadhaniya <quic_vdadhani@quicinc.com> Link: https://lore.kernel.org/r/20240215090910.30021-1-quic_vdadhani@quicinc.comSigned-off-by:
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Ankit Sharma authored
The "capacity-dmips-mhz" and "dynamic-power-coefficient" are used to build Energy Model which in turn is used by EAS to take placement decisions. So add it to SC7280 soc. Signed-off-by:
Ankit Sharma <quic_anshar@quicinc.com> Reviewed-by:
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Luca Weiss authored
With SDAM + PBS the LPG driver can configure the LED pattern in hardware. Signed-off-by:
Luca Weiss <luca.weiss@fairphone.com> Link: https://lore.kernel.org/r/20240205-pmi632-ppg-v1-2-e236c95a2099@fairphone.comSigned-off-by:
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Neil Armstrong authored
Both PCIe0 and PCIe1 controllers are capable of signalling the MSIs received from endpoint devices to the CPU using GIC-ITS MSI controller. Add support for it. The GIC-ITS MSI implementation provides an advantage over internal MSI implementation using Locality-specific Peripheral Interrupts (LPI) that would allow MSIs to be targeted for each CPU core. Like SM8450, the IDs are swapped, but works fine on PCIe0 and PCIe1. WiFi PCIe Device on SM8550-QRD using GIC-ITS: 218: 0 4 0 0 0 0 0 0 ITS-MSI 524288 Edge bhi 219: 0 0 5 0 0 0 0 0 ITS-MSI 524289 Edge mhi 220: 0 0 0 33 0 0 0 0 ITS-MSI 524290 Edge mhi 221: 0 0 0 0 3 0 0 0 ITS-MSI 524291 Edge ce0 222: 0 0 0 0 0 1 0 0 ITS-MSI 524292 Edge ce1 223: 0 0 0 0 0 0 38 0 ITS-MSI 524293 Edge ce2 224: 0 0 0 0 0 0 0 31 ITS-MSI 524294 Edge ce3 225: 0 0 0 0 0 0 0 0 ITS-MSI 524295 Edge ce5 226: 0 0 0 0 0 0 0 0 ITS-MSI 524296 Edge DP_EXT_IRQ 227: 0 0 0 0 0 0 0 0 ITS-MSI 524297 Edge DP_EXT_IRQ 228: 0 0 0 0 0 0 0 0 ITS-MSI 524298 Edge DP_EXT_IRQ 229: 0 0 0 0 0 0 0 0 ITS-MSI 524299 Edge DP_EXT_IRQ 230: 0 0 0 0 0 0 0 0 ITS-MSI 524300 Edge DP_EXT_IRQ 231: 0 0 0 0 0 0 0 0 ITS-MSI 524301 Edge DP_EXT_IRQ 232: 0 0 0 0 0 0 0 0 ITS-MSI 524302 Edge DP_EXT_IRQ NVMe in SM8550-HDK M.2 Slot using GIC-ITS: 212: 0 0 22 0 0 0 0 0 ITS-MSI 134742016 Edge nvme0q0 213: 133098 0 0 0 0 0 0 0 ITS-MSI 134742017 Edge nvme0q1 214: 0 139450 0 0 0 0 0 0 ITS-MSI 134742018 Edge nvme0q2 215: 0 0 139476 0 0 0 0 0 ITS-MSI 134742019 Edge nvme0q3 216: 0 0 0 69767 0 0 0 0 ITS-MSI 134742020 Edge nvme0q4 217: 0 0 0 0 80368 0 0 0 ITS-MSI 134742021 Edge nvme0q5 218: 0 0 0 0 0 77315 0 0 ITS-MSI 134742022 Edge nvme0q6 219: 0 0 0 0 0 0 73022 0 ITS-MSI 134742023 Edge nvme0q7 220: 0 0 0 0 0 0 0 329993 ITS-MSI 134742024 Edge nvme0q8 Signed-off-by:
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Krzysztof Kozlowski authored
Bindings allow a "wake", not "enable", GPIO. Schematics also use WAKE name for the pin: sa8155p-adp.dtb: pcie@1c00000: Unevaluated properties are not allowed ('enable-gpio' was unexpected) Fixes: a1c86c68 ("arm64: dts: qcom: sm8150: Add PCIe nodes") Signed-off-by: -
Krzysztof Kozlowski authored
Bindings allow a "wake", not "enable", GPIO. Schematics also use WAKE name for the pin: sdm845-db845c.dtb: pcie@1c00000: Unevaluated properties are not allowed ('enable-gpio' was unexpected) Fixes: 4a657c26 ("arm64: dts: qcom: db845c: Enable PCIe controllers") Signed-off-by: -
Luca Weiss authored
Add the description for the display panel found on this phone. Unfortunately the LCDB module on PM6150L isn't yet supported upstream so we need to use a dummy regulator-fixed in the meantime. And with this done we can also enable the GPU and set the zap shader firmware path. Reviewed-by:
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Luca Weiss authored
The GMU won't probe without GPU being enabled, so we can remove the disabled status so we don't have to explicitly enable the GMU in all the devices that enable GPU. Reviewed-by:
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Joe Mason authored
Like the Samsung Galaxy A3/A5, the Grand Prime/Core Prime uses a Richtek RT5033 PMIC as battery fuel gauge, charger, flash LED and for some regulators. For now, only add the fuel gauge/battery device to the device tree, so we can check the remaining battery percentage. The other RT5033 drivers need some more work first before they can be used properly. Signed-off-by:
Joe Mason <buddyjojo06@outlook.com> [Raymond: Move to fortuna-common. Use interrupts-extended] Signed-off-by:
Raymond Hackley <raymondhackley@protonmail.com> Reviewed-by:
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Luca Weiss authored
Add the definition for the interconnect used in the display subsystem. Signed-off-by:
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- 14 Feb, 2024 14 commits
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Walter Broemeling authored
Samsung Galaxy Core Prime and Grand Prime are phones based on MSM8916. They are similar to the other Samsung devices based on MSM8916 with only a few minor differences. This initial commit adds support for: - fortuna3g (SM-G530H) - gprimeltecan (SM-G530W) - grandprimelte (SM-G530FZ) - rossa (SM-G360G) The device trees contain initial support with: - GPIO keys - Regulator haptic - SDHCI (internal and external storage) - USB Device Mode - UART (on USB connector via the SM5502/SM5504 MUIC) - WCNSS (WiFi/BT) - Regulators - QDSP6 audio - Speaker/earpiece/headphones/microphones via digital/analog codec in MSM8916/PM8916 - WWAN Internet via BAM-DMUX There are different variants of Core Prime and Grand Prime, with some differences in accelerometer, NFC and panel. Core Prime and Grand Prime are similar, with some differences in MUIC, panel and touchscreen. The common parts are shared in msm8916-samsung-fortuna-common.dtsi and msm8916-samsung-rossa-common.dtsi to reduce duplication. Signed-off-by:
Walter Broemeling <wallebroem@gmail.com> Signed-off-by:
Stephan Gerhold <stephan@gerhold.net> [Joe: Add audio, buttons and WiFi] Signed-off-by:
Siddharth Manthan <siddharth.manthan@gmail.com> [Raymond: Add modem, fortuna-common.dtsi, grandprimelte and rossa] Signed-off-by:
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Konrad Dybcio authored
Now that the non-legacy form of OPP is supported within the UFS driver, go ahead and switch to it, adding support for more intermediate freq/power states. Signed-off-by:
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Krzysztof Kozlowski authored
Each group of MSI interrupts is mapped to the separate host interrupt. Describe each of interrupts in the device tree for PCIe hosts. This also corrects PCIe1 and PCIe2 first MSI interrupt. Signed-off-by:
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Krzysztof Kozlowski authored
The DTS code coding style expects exactly one space before '{' and around '=' characters. Signed-off-by: -
Krzysztof Kozlowski authored
Neither bindings nor UFS phy driver use properties like 'vdda-phy-max-microamp' and 'vdda-pll-max-microamp': sm7125-xiaomi-curtana.dtb: phy@1d87000: 'vdda-phy-max-microamp', 'vdda-pll-max-microamp' do not match any of the regexes: 'pinctrl-[0-9]+' Signed-off-by:
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Krzysztof Kozlowski authored
Add sound card to X1E80100-CRD board and update DMIC supply. Works so far: - Audio playback via speakers or audio jack headset, - DMIC0-3 recording. Reviewed-by:
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Krzysztof Kozlowski authored
Correct the TLMM pin configuration and muxing node names used for DMIC2 and DMIC3 (dmic01 -> dmic23). This has no functional impact, but improves code readability and avoids any confusion when reading the DTS. Signed-off-by:
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Krzysztof Kozlowski authored
Correct the TLMM pin configuration and muxing node names used for DMIC2 and DMIC3 (dmic01 -> dmic23). This has no functional impact, but improves code readability and avoids any confusion when reading the DTS. Signed-off-by:
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Krzysztof Kozlowski authored
Correct the TLMM pin configuration and muxing node names used for DMIC2 and DMIC3 (dmic01 -> dmic23). This has no functional impact, but improves code readability and avoids any confusion when reading the DTS. Signed-off-by:
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Krzysztof Kozlowski authored
Correct the TLMM pin configuration and muxing node names used for DMIC2 and DMIC3 (dmic01 -> dmic23). This has no functional impact, but improves code readability and avoids any confusion when reading the DTS. Signed-off-by:
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Krzysztof Kozlowski authored
Correct the TLMM pin configuration and muxing node names used for DMIC2 and DMIC3 (dmic01 -> dmic23). This has no functional impact, but improves code readability and avoids any confusion when reading the DTS. Signed-off-by:
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Mark Hasemeyer authored
The cros_ec driver currently assumes that cros-ec-spi compatible device nodes are a wakeup-source even though the wakeup-source property is not defined. Some Chromebooks use a separate wake pin, while others overload the interrupt for wake and IO. With the current assumption, spurious wakes can occur on systems that use a separate wake pin. It is planned to update the driver to no longer assume that the EC interrupt pin should be enabled for wake. Add the wakeup-source property to all cros-ec-spi compatible device nodes to signify to the driver that they should still be a valid wakeup source. Reviewed-by:
Mark Hasemeyer <markhas@chromium.org> Link: https://lore.kernel.org/r/20240102140734.v4.16.I870e2c3490e7fc27a8f6bc41dba23b3dfacd2d13@changeidSigned-off-by:
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Mark Hasemeyer authored
The cros_ec driver currently assumes that cros-ec-spi compatible device nodes are a wakeup-source even though the wakeup-source property is not defined. Some Chromebooks use a separate wake pin, while others overload the interrupt for wake and IO. With the current assumption, spurious wakes can occur on systems that use a separate wake pin. It is planned to update the driver to no longer assume that the EC interrupt pin should be enabled for wake. Add the wakeup-source property to all cros-ec-spi compatible device nodes to signify to the driver that they should still be a valid wakeup source. Reviewed-by:
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Mark Hasemeyer authored
The cros_ec driver currently assumes that cros-ec-spi compatible device nodes are a wakeup-source even though the wakeup-source property is not defined. Some Chromebooks use a separate wake pin, while others overload the interrupt for wake and IO. With the current assumption, spurious wakes can occur on systems that use a separate wake pin. It is planned to update the driver to no longer assume that the EC interrupt pin should be enabled for wake. Add the wakeup-source property to all cros-ec-spi compatible device nodes to signify to the driver that they should still be a valid wakeup source. Reviewed-by:
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