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  1. 19 Oct, 2021 2 commits
    • Arnd Bergmann's avatar
      Merge tag 'qcom-dts-for-5.16' of... · 878e26d3
      Arnd Bergmann authored 
      Merge tag 'qcom-dts-for-5.16' of git://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into arm/dt

Qualcomm DTS updates for v5.16

This extends the previous limited description of MSM8226 with SDHC,
UART, I2C, SCM, SMEM, RPM and basic PMIC definitions. Based on this,
initial support for the LG G Watch R smartwatch is introduced.

APQ8064 gets a couple of DT updates, one which will allow the GPU driver
to drop supporting legacy "opp tables" in the future.

DT bindings and DTS files are updated with additional compatibles, for
completeness.

* tag 'qcom-dts-for-5.16' of git://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux:
  dt-bindings: arm: qcom, add missing devices
  ARM: dts: qcom: msm8974: Add xo_board reference clock to DSI0 PHY
  ARM: dts: qcom: fill secondary compatible for multiple boards
  ARM: dts: qcom: apq8064: adjust memory node according to specs
  ARM: dts: qcom: apq8064: Convert adreno from legacy gpu-pwrlevels to opp-v2
  ARM: dts: qcom: Add support for LG G Watch R
  dt-bindings: arm: qcom: Document APQ8026 SoC binding
  ARM: dts: qcom: Add pm8226 PMIC
  ARM: dts: qcom: msm8226: Add more SoC bits
  dt-bindings: arm: qcom: Document SDX65 platform and boards

Link: https://lore.kernel.org/r/20211012174310.1017857-1-bjorn.andersson@linaro.orgSigned-off-by: default avatarArnd Bergmann <arnd@arndb.de>
      878e26d3
    • Arnd Bergmann's avatar
      Merge tag 'v5.15-next-dts64' of... · ba232d39
      Arnd Bergmann authored 
      Merge tag 'v5.15-next-dts64' of git://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux into arm/dt

Biggest change is, that we have now support for a reset controller inside the
mmsys. This goes inhand with changes to the driver, that you will find in the
soc pull request.

Mediatek PCI device tree binding described the root port in a wrong. The IP
actaully implements several root complex with everyone having a single root port.

We need to fix the DT in an incompatible way to describe the HW as it is. This
also fixes a problem that no IRQ bigger then 32 could be handled.

The only public available HW that is affected by this is the BananaPi R64. I'm
not aware that there is a big user base using the upstream kernel. In this
boards PCI is only used for extension cards, so I don't expect any boot problems.

- mt8173: add reset for dsi0 to mmsys
- move dt-bindings reset controller includes to correct folder
- split PCIe node to use new format for mt2712 and mt7622
- mt8183: add audio node to chromebook devices
- mt8192: add clock controller node

* tag 'v5.15-next-dts64' of git://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux:
  arm64: dts: mt8183: Add the mmsys reset bit to reset the dsi0
  arm64: dts: mt8173: Add the mmsys reset bit to reset the dsi0
  dt-bindings: display: mediatek: add dsi reset optional property
  dt-bindings: mediatek: Add #reset-cells to mmsys system controller
  arm64: dts: mediatek: Move reset controller constants into common location
  arm64: dts: mediatek: Split PCIe node for MT2712 and MT7622
  arm64: dts: mt8183: add kukui platform audio node
  arm64: dts: mt8183: add audio node
  arm64: dts: mediatek: Add mt8192 clock controllers

Link: https://lore.kernel.org/r/1a3d63a3-c020-3319-26f6-a2ec338cc42e@gmail.comSigned-off-by: default avatarArnd Bergmann <arnd@arndb.de>
      ba232d39
  3. 12 Oct, 2021 1 commit
    • Arnd Bergmann's avatar
      Merge tag 'ti-k3-dt-for-v5.16' of... · 96c7f32d
      Arnd Bergmann authored 
      Merge tag 'ti-k3-dt-for-v5.16' of git://git.kernel.org/pub/scm/linux/kernel/git/nmenon/linux into arm/dt

Devicetree changes for TI K3 platforms for v5.16 merge window:

* New Platforms:
  - AM654: Siemens IOT2050 PG2 boards
  - J721E: Low cost SK board
* New features:
  - mmc aliases introduced
  - AM64 ICSSG nodes, mcu pinctrl added
* Fixes:
  - Schema fixups for pcie, thermal zones
  - Fixup to include board specific property for J721e-evm and j7200-evm
  - Misc fixups including cleaning up order in Makefile

* tag 'ti-k3-dt-for-v5.16' of git://git.kernel.org/pub/scm/linux/kernel/git/nmenon/linux: (24 commits)
  arm64: dts: ti: k3-j721e-sk: Add DDR carveout memory nodes
  arm64: dts: ti: k3-j721e-sk: Add IPC sub-mailbox nodes
  arm64: dts: ti: Add support for J721E SK
  dt-bindings: arm: ti: Add compatible for J721E SK
  arm64: dts: ti: iot2050: Add support for product generation 2 boards
  arm64: dts: ti: iot2050: Prepare for adding 2nd-generation boards
  dt-bindings: arm: ti: Add bindings for Siemens IOT2050 PG2 boards
  arm64: dts: ti: iot2050: Add/enabled mailboxes and carve-outs for R5F cores
  arm64: dts: ti: iot2050: Disable SR2.0-only PRUs
  arm64: dts: ti: iot2050: Flip mmc device ordering on Advanced devices
  arm64: dts: ti: k3-j7200-common-proc-board: Add j7200-evm compatible
  arm64: dts: ti: k3-j721e-common-proc-board: Add j721e-evm compatible
  dt-bindings: arm: ti: Add missing compatibles for j721e/j7200 evms
  arm64: dts: ti: Makefile: Collate AM64 platforms together
  arm64: dts: ti: k3-am64-main: Add ICSSG nodes
  arm64: dts: ti: k3-am65: Relocate thermal-zones to SoC specific location
  arm64: dts: ti: ti-k3*: Introduce aliases for mmc nodes
  arm64: dts: ti: k3-am65-main: Cleanup "ranges" property in "pcie" DT node
  arm64: dts: ti: j7200-main: Add *max-virtual-functions* for pcie-ep DT node
  arm64: dts: ti: j7200-main: Fix "bus-range" upto 256 bus number for PCIe
  ...

Link: https://lore.kernel.org/r/20211012120817.beqhp4tygnf3xyi5@wirelessSigned-off-by: default avatarArnd Bergmann <arnd@arndb.de>
      96c7f32d
  5. 11 Oct, 2021 11 commits
  7. 08 Oct, 2021 6 commits
  9. 07 Oct, 2021 8 commits
  11. 06 Oct, 2021 10 commits
  13. 05 Oct, 2021 2 commits
    • Sinthu Raja's avatar
      arm64: dts: ti: k3-j721e-sk: Add DDR carveout memory nodes · f46d16cf
      Sinthu Raja authored 
      Two carveout reserved memory nodes each have been added for each of the
other remote processors devices within the MAIN domain on the TI J721E
SK boards. These nodes are assigned to the respective rproc device nodes
as well. The first region will be used as the DMA pool for the rproc
devices, and the second region will furnish the static carveout regions
for the firmware memory.

An additional reserved memory node is also added to reserve a portion of
the DDR memory to be used for performing inter-processor communication
between all the remote processors running RTOS or baremetal firmwares.
8 MB of memory is reserved for this purpose, and this accounts for all
the vrings and vring buffers between all the possible pairs of remote
processors.

The current carveout addresses and sizes are defined statically for each
rproc device. The R5F processors do not have an MMU, and as such require
the exact memory used by the firmwares to be set-aside. The C71x DSP
processor does support a MMU called CMMU, but is not currently supported
and as such requires the exact memory used by the firmware to be
set-aside. The firmware images do not require any RSC_CARVEOUT entries
in their resource tables to allocate the memory for firmware memory
segments
Signed-off-by: default avatarSinthu Raja <sinthu.raja@ti.com>
Signed-off-by: default avatarNishanth Menon <nm@ti.com>
Link: https://lore.kernel.org/r/20210929081333.26454-5-sinthu.raja@ti.com
      f46d16cf
    • Sinthu Raja's avatar
      arm64: dts: ti: k3-j721e-sk: Add IPC sub-mailbox nodes · e910e5b6
      Sinthu Raja authored 
      Add the sub-mailbox nodes that are used to communicate between MPU and
various remote processors present in the J721E SoCs to the J721E EAIK
board. These include the R5F remote processors in the dual-R5F cluster
(MCU_R5FSS0) in the MCU domain and the two dual-R5F clusters
(MAIN_R5FSS0 & MAIN_R5FSS1) in the MAIN domain; the two C66x DSP remote
processors and the single C71x DSP remote processor in the MAIN domain.
These sub-mailbox nodes utilize the System Mailbox clusters 0 through 4.
All the remaining mailbox clusters are currently not used on A72 core,
and are hence disabled.

The sub-mailbox nodes added match the hard-coded mailbox configuration
used within the TI RTOS IPC software packages. The R5F processor
sub-systems are assumed to be running in Split mode, so a sub-mailbox
node is used by each of the R5F cores. Only the sub-mailbox node for
the first R5F core in each cluster is used in case of a Lockstep mode
for that R5F cluster.
Signed-off-by: default avatarSinthu Raja <sinthu.raja@ti.com>
Signed-off-by: default avatarNishanth Menon <nm@ti.com>
Link: https://lore.kernel.org/r/20210929081333.26454-4-sinthu.raja@ti.com
      e910e5b6
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