* lorenzo/pci/rcar:
  PCI: rcar: Handle rcar_pcie_parse_request_of_pci_ranges() failures

* lorenzo/pci/keystone:
  PCI: keystone: Fix interrupt-controller-node lookup

* lorenzo/pci/endpoint:
  PCI: endpoint: Use EPC's device in dma_alloc_coherent()/dma_free_coherent()
  PCI: designware-ep: Fix ->get_msi() to check MSI_EN bit
  PCI: endpoint: Fix find_first_zero_bit() usage
  PCI: endpoint: Populate func_no before calling pci_epc_add_epf()
  PCI: designware-ep: Fix find_first_zero_bit() usage

* lorenzo/pci/dwc:
  PCI: exynos: Fix a potential init_clk_resources NULL pointer dereference
  PCI: iproc: Fix NULL pointer dereference for BCMA
  PCI: dra7xx: Iterate over INTx status bits
  PCI: dra7xx: Fix legacy INTD IRQ handling
  PCI: qcom: Account for const type of of_device_id.data
  PCI: dwc: artpec6: Fix return value check in artpec6_add_pcie_ep()
  PCI: exynos: Remove deprecated PHY initialization code
  PCI: dwc: artpec6: Add support for the ARTPEC-7 SoC
  bindings: PCI: artpec: Add support for the ARTPEC-7 SoC
  PCI: dwc: artpec6: Deassert the core before waiting for PHY
  PCI: dwc: Make cpu_addr_fixup take struct dw_pcie as argument
  PCI: dwc: artpec6: Add support for endpoint mode
  bindings: PCI: artpec: Add support for endpoint mode
  PCI: dwc: artpec6: Split artpec6_pcie_establish_link() into smaller functions
  PCI: dwc: artpec6: Use BIT and GENMASK macros
  PCI: dwc: artpec6: Remove unused defines
  PCI: dwc: dra7xx: Help compiler to remove unused code
  PCI: dwc: dra7xx: Assign pp->ops in dra7xx_add_pcie_port() rather than in probe
  PCI: dwc: dra7xx: Refactor Kconfig and Makefile handling for host/ep mode
  PCI: designware-ep: Add generic function for raising MSI irq
  PCI: designware-ep: Remove static keyword from dw_pcie_ep_reset_bar()
  PCI: designware-ep: Pre-allocate memory for MSI in dw_pcie_ep_init
  PCI: designware-ep: Read-only registers need DBI_RO_WR_EN to be writable
  PCI: designware-ep: dw_pcie_ep_set_msi() should only set MMC bits
  PCI: dwc: Use the DMA-API to get the MSI address
  pci: dwc: pci-dra7xx: Make shutdown handler static

Includes resolution to conflict between:

  4494738d ("PCI: endpoint: Add the function number as argument to EPC ops")
  6f6d7873 ("PCI: designware-ep: Add generic function for raising MSI irq")

The resolution is due to Niklas Cassel <niklas.cassel@axis.com>:
https://lkml.kernel.org/r/20180201085608.GA22568@axis.com

* lorenzo/pci/cadence:
  PCI: cadence: Add EndPoint Controller driver for Cadence PCIe controller
  dt-bindings: PCI: cadence: Add DT bindings for Cadence PCIe endpoint controller
  PCI: endpoint: Fix EPF device name to support multi-function devices
  PCI: endpoint: Add the function number as argument to EPC ops
  PCI: cadence: Add host driver for Cadence PCIe controller
  dt-bindings: PCI: cadence: Add DT bindings for Cadence PCIe host controller
  PCI: Add vendor ID for Cadence
  PCI: Add generic function to probe PCI host controllers
  PCI: generic: fix missing call of pci_free_resource_list()
  PCI: OF: Add generic function to parse and allocate PCI resources
  PCI: Regroup all PCI related entries into drivers/pci/Makefile

Conflicts:
	drivers/pci/of.c
	include/linux/pci.h

* pci/virtualization:
  PCI: Expose ari_enabled in sysfs
  PCI: Add function 1 DMA alias quirk for Marvell 9128
  PCI: Mark Ceton InfiniTV4 INTx masking as broken
  xen/pci: Use acpi_noirq_set() helper to avoid #ifdef

* pci/trivial:
  PCI: Clean up whitespace in linux/pci.h, pci/pci.h
  PCI: Tidy up pci/probe.c comments

* pci/switchtec:
  switchtec: Add device IDs for PSX 24xG3 and PSX 48xG3
  switchtec: Add Global Fabric Manager Server (GFMS) event

* pci/resource:
  PCI: tegra: Remove PCI_REASSIGN_ALL_BUS use on Tegra
  resource: Set type when reserving new regions
  resource: Set type of "reserve=" user-specified resources
  irqchip/i8259: Set I/O port resource types correctly
  powerpc: Set I/O port resource types correctly
  MIPS: Set I/O port resource types correctly
  vgacon: Set VGA struct resource types
  PCI: Use dev_info() rather than dev_err() for ROM validation
  PCI: Remove PCI_REASSIGN_ALL_RSRC use on arm and arm64
  PCI: Remove sysfs resource mmap warning

Conflicts:
	drivers/pci/rom.c

* pci/msi:
  PCI: Disable MSI for HiSilicon Hip06/Hip07 only in Root Port mode

* pci/misc:
  PCI: Add dummy pci_irqd_intx_xlate() for CONFIG_PCI=n build
  PCI: Add wrappers for dev_printk()
  PCI: Remove unnecessary messages for memory allocation failures
  PCI: Add #defines for Completion Timeout Disable feature
  hinic: Replace PCI pool old API
  net: e100: Replace PCI pool old API
  block: DAC960: Replace PCI pool old API
  MAINTAINERS: Include more PCI files
  PCI: Remove unneeded kallsyms include
  powerpc/pci: Unroll two pass loop when scanning bridges
  powerpc/pci: Use for_each_pci_bridge() helper

* pci/hotplug:
  PCI: pciehp: Assume NoCompl+ for Thunderbolt ports
  PCI: hotplug: Drop checking of PCI_BRIDGE_CONTROL in *_unconfigure_device()

* pci/enumeration:
  RDMA/qedr: Use pci_enable_atomic_ops_to_root()
  PCI: Add pci_enable_atomic_ops_to_root()
  PCI: Make PCI_SCAN_ALL_PCIE_DEVS work for Root as well as Downstream Ports

* pci/dt-resources:
  PCI: Make of_irq_parse_pci() static
  powerpc/pci: Use of_irq_parse_and_map_pci() helper
  PCI: Move OF-related PCI functions into PCI core

* pci/dpc:
  PCI/DPC: Reformat DPC register definitions
  PCI/DPC: Add and use DPC Status register field definitions
  PCI/DPC: Squash dpc_rp_pio_get_info() into dpc_process_rp_pio_error()
  PCI/DPC: Remove unnecessary RP PIO register structs
  PCI/DPC: Push dpc->rp_pio_status assignment into dpc_rp_pio_get_info()
  PCI/DPC: Squash dpc_rp_pio_print_error() into dpc_rp_pio_get_info()
  PCI/DPC: Make RP PIO log size check more generic
  PCI/DPC: Rename local "status" to "dpc_status"
  PCI/DPC: Squash dpc_rp_pio_print_tlp_header() into dpc_rp_pio_print_error()
  PCI/DPC: Process RP PIO details only if RP PIO extensions supported
  PCI/DPC: Read RP PIO Log Size once at probe
  PCI/DPC: Rename struct dpc_dev.rp to rp_extensions
  PCI/DPC: Add local variable for DPC capability offset
  PCI/DPC: Rename interrupt_event_handler() to dpc_work()
  PCI/DPC: Fix interrupt message number print
  PCI/DPC: Enable DPC only if AER is available
  PCI/DPC: Fix shared interrupt handling

* pci/dma:
  PCI: Remove NULL device handling from PCI DMA API
  net: tsi108: Use DMA API properly
  media: ttusb-dec: Remove pci_zalloc_coherent() abuse
  media: ttusb-budget: Remove pci_zalloc_coherent() abuse

* pci/deprecate-get-bus-and-slot:
  video: fbdev: riva: deprecate pci_get_bus_and_slot()
  video: fbdev: nvidia: deprecate pci_get_bus_and_slot()
  video: fbdev: intelfb: deprecate pci_get_bus_and_slot()
  openprom: Deprecate pci_get_bus_and_slot()
  xen/pcifront: Deprecate pci_get_bus_and_slot()
  PCI: Deprecate pci_get_bus_and_slot()
  PCI: ibmphp: Deprecate pci_get_bus_and_slot()
  PCI: cpqhp: Deprecate pci_get_bus_and_slot()
  pch_gbe: Deprecate pci_get_bus_and_slot()
  bnx2x: Deprecate pci_get_bus_and_slot()
  powerpc/via-pmu: Deprecate pci_get_bus_and_slot()
  iommu/amd: Deprecate pci_get_bus_and_slot()
  sl82c105: deprecate pci_get_bus_and_slot()
  drm/nouveau: deprecate pci_get_bus_and_slot()
  drm/gma500: Deprecate pci_get_bus_and_slot()
  ibft: Deprecate pci_get_bus_and_slot()
  edd: Deprecate pci_get_bus_and_slot()
  agp: sworks: Deprecate pci_get_bus_and_slot()
  agp: nvidia: Deprecate pci_get_bus_and_slot()
  ata: Deprecate pci_get_bus_and_slot()
  x86/PCI: Deprecate pci_get_bus_and_slot()
  powerpc/PCI: Deprecate pci_get_bus_and_slot()
  alpha/PCI: Deprecate pci_get_bus_and_slot()

* pci/aspm:
  PCI/ASPM: Unexport internal ASPM interfaces
  PCI/ASPM: Enable Latency Tolerance Reporting when supported
  PCI/ASPM: Calculate LTR_L1.2_THRESHOLD from device characteristics

* pci/aer:
  PCI/AER: Return error if AER is not supported
  PCI/AER: Skip recovery callbacks for correctable errors from ACPI APEI

This patch adds support to the Cadence PCIe controller in endpoint mode.

Since pieces of source code are shared with the host driver (Root
Complex mode), we create a new directory under drivers/pci dedicated to
the Cadence PCIe controller. The common code is placed into
drivers/pci/cadence/pcie-cadence.c and used by both the host and
endpoint controller drivers.
Signed-off-by: Cyrille Pitchen <cyrille.pitchen@free-electrons.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>

This patch documents the DT bindings for the Cadence PCIe controller
when configured in endpoint mode.
Signed-off-by: Cyrille Pitchen <cyrille.pitchen@free-electrons.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: Rob Herring <robh@kernel.org>

Fix the pci_epf_make() function so it can now bind many EPF devices to the
same EPF driver.
Signed-off-by: Cyrille Pitchen <cyrille.pitchen@free-electrons.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>

This patch updates the prototype of most handlers from 'struct
pci_epc_ops' so the EPC library can now support multi-function devices.
Signed-off-by: Cyrille Pitchen <cyrille.pitchen@free-electrons.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>

This patch adds support to the Cadence PCIe controller in host mode.
Signed-off-by: Cyrille Pitchen <cyrille.pitchen@free-electrons.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>

This patch adds documentation for the DT bindings of the Cadence PCIe
controller when configured in host (Root Complex) mode.
Signed-off-by: Scott Telford <stelford@cadence.com>
Signed-off-by: Cyrille Pitchen <cyrille.pitchen@free-electrons.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: Rob Herring <robh@kernel.org>

This patch adds a new PCI vendor ID for Cadence.
Signed-off-by: Cyrille Pitchen <cyrille.pitchen@free-electrons.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>

This patchs moves generic source code from
drivers/pci/host/pci-host-common.c into drivers/pci/probe.c.

Indeed the extracted lines of code were duplicated by many host
controller drivers. Regrouping them into a generic function gives a
change to properly share this code without introducing a useless
dependency to PCI_HOST_COMMON, which selects PCI_ECAM when not needed by
most host controller drivers.
Signed-off-by: Cyrille Pitchen <cyrille.pitchen@free-electrons.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>

Call pci_free_resource_list() from pci_host_common_probe() when probing
fails, as done inside gen_pci_init() when this later function fails.
Signed-off-by: Cyrille Pitchen <cyrille.pitchen@free-electrons.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>

The patch moves the gen_pci_parse_request_of_pci_ranges() function from
drivers/pci/host/pci-host-common.c into drivers/pci/of.c to easily share
common source code between PCI host drivers.
Signed-off-by: Cyrille Pitchen <cyrille.pitchen@free-electrons.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>

Clean up drivers/Makefile by moving the pci/endpoint and pci/dwc entries
from drivers/Makefile into drivers/pci/Makefile.

Since we don't want to introduce any dependency between CONFIG_PCI and
CONFIG_PCI_ENDPOINT, we now always execute drivers/pci/Makefile.

Hence all Makefiles in drivers/pci/ were updated accordingly so no file is
compiled when CONFIG_PCI is not defined.

Also, we add a comment to reinforce that EPC and EPF libraries must be
initialized before their users. Hence built-in EPC drivers, such as
those of Designware, are linked after the endpoint core libraries.

Finally, we add another comment to explain why obj-y has been chosen
instead of obj-$(CONFIG_PCIE_DW) to parse the dwc/ sub-folder.
Signed-off-by: Cyrille Pitchen <cyrille.pitchen@free-electrons.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>

Reformat DPC register definitions to follow the convention that register
field masks indicate the register width, e.g., a field of a 16-bit register
uses a mask of 4 hex digits, with leading zeros included as needed.
No functional change intended.
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Keith Busch <keith.busch@intel.com>
Reviewed-by: Sinan Kaya <okaya@codeaurora.org>

Add definitions for DPC Status register fields and use them in the code.
No functional change intended.
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Keith Busch <keith.busch@intel.com>
Reviewed-by: Sinan Kaya <okaya@codeaurora.org>

dpc_process_rp_pio_error() only calls dpc_rp_pio_get_info(), so squash them
together.  No functional change intended.
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Keith Busch <keith.busch@intel.com>
Reviewed-by: Sinan Kaya <okaya@codeaurora.org>

We read and immediately print the RP PIO log registers.  We don't save
them, so there's no need to define structs for them.  Remove the structs
and read the registers into local variables instead.  No functional change
intended.
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Keith Busch <keith.busch@intel.com>
Reviewed-by: Sinan Kaya <okaya@codeaurora.org>

Move the dpc->rp_pio_status assignment into dpc_rp_pio_get_info() since
that's where we read rp_pio->status anway.  No functional change intended.
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Keith Busch <keith.busch@intel.com>
Reviewed-by: Sinan Kaya <okaya@codeaurora.org>

Separating dpc_rp_pio_print_error() doesn't really provide any useful
abstraction, so squash it into its caller, dpc_rp_pio_get_info().  No
functional change intended.
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Keith Busch <keith.busch@intel.com>
Reviewed-by: Sinan Kaya <okaya@codeaurora.org>

In dpc_probe(), we set dpc->rp_log_size to zero if we think the hardware
reports an invalid size.  In this case, we could have dpc->rp_extensions
set but dpc->rp_log_size == 0, and we should print the basic RP PIO
registers but not the variable-size portion.  We already checked for
dpc->rp_log_size < 4 above, so this patch is just for consistency of style.
No functional change intended.
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Keith Busch <keith.busch@intel.com>
Reviewed-by: Sinan Kaya <okaya@codeaurora.org>

In dpc_rp_pio_get_info() rename the local "status" variable to
"dpc_status".  This is to make room for another variable named "status" in
a subsequent patch.  No functional change intended.
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Keith Busch <keith.busch@intel.com>
Reviewed-by: Sinan Kaya <okaya@codeaurora.org>

Separating dpc_rp_pio_print_tlp_header() doesn't really provide any useful
abstraction, so squash it into its caller, dpc_rp_pio_print_error().  No
functional change intended.
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Keith Busch <keith.busch@intel.com>
Reviewed-by: Sinan Kaya <okaya@codeaurora.org>

The RP PIO registers (status, mask, severity, etc) are only implemented if
the "RP Extensions for DPC" bit is set in the DPC Capabilities register.

Previously we called dpc_process_rp_pio_error(), which reads and decodes
those RP PIO registers, whenever the DPC Status register indicated an "RP
PIO error" (Trigger Reason == 3 and Trigger Reason Extension == 0).

It does seem reasonable to assume that DPC Status would only indicate an RP
PIO error if the RP extensions are supported, but PCIe r4.0, sec 7.9.15.4,
is actually not explicit about that: it does not say "Trigger Reason
Extension == 0 is valid only for Root Ports that support RP Extensions for
DPC."

Check whether the RP Extensions for DPC are supported before trying to read
the RP PIO registers.
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Keith Busch <keith.busch@intel.com>
Reviewed-by: Sinan Kaya <okaya@codeaurora.org>